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74HC373PW

HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20

器件类别：逻辑    逻辑   

厂商名称：Philips Semiconductors (NXP Semiconductors N.V.)

厂商官网：https://www.nxp.com/

器件标准：

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Philips Semiconductors (NXP Semiconductors N.V.)
包装说明
TSSOP, TSSOP20,.25
Reach Compliance Code
unknow
JESD-30 代码
R-PDSO-G20
负载电容（CL）
50 pF
逻辑集成电路类型
D LATCH
最大I（ol）
0.006 A
位数
8
功能数量
1
端子数量
20
最高工作温度
125 °C
最低工作温度
-40 °C
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP20,.25
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法
TUBE
电源
2/6 V
Prop。Delay @ Nom-Su
45 ns
认证状态
Not Qualified
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子形式
GULL WING
端子节距
0.635 mm
端子位置
DUAL
Base Number Matches
1
文档预览
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT373
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES
•
3-state non-inverting outputs for bus oriented
applications
•
Common 3-state output enable input
•
Functionally identical to the “563”, “573” and “533”
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT373 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT373 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT373
input and an output enable (OE) input are common to all
latches.
The “373” consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the D
n
inputs enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “373” is functionally identical to the “533”, “563” and
“573”, but the “563” and “533” have inverted outputs and
the “563” and “573” have a different pin arrangement.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
D
n
to Q
n
LE to Q
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
. For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
15
3.5
45
14
13
3.5
41
ns
ns
pF
pF
HCT
UNIT
September 1993
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
OE
Q
0
to Q
7
D
0
to D
7
GND
LE
V
CC
NAME AND FUNCTION
74HC/HCT373
3-state output enable input (active LOW)
3-state latch outputs
data inputs
ground (0 V)
latch enable input (active HIGH)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE
INPUTS
OPERATING
MODES
OE LE D
n
enable and
read
register
(transparent
mode)
latch and
read register
latch register
and disable
outputs
Fig.4 Functional diagram.
Notes
L
L
H
H
L
H
74HC/HCT373
INTERNAL
LATCHES
L
H
OUTPUTS
Q
0
to Q
7
L
H
L
L
H
H
L
L
X
X
l
h
X
X
L
H
X
X
L
H
Z
Z
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
Fig.5 Logic diagram (one latch).
Fig.6 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to
+125
max.
225
45
38
265
53
45
225
45
38
225
45
38
90
18
15
120
24
20
75
15
13
5
5
5
ns
74HC/HCT373
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
propagation delay
LE to Q
n
3-state output enable time
OE to Q
n
3-state output disable time
OE to Q
n
output transition time
41
15
12
50
18
14
44
16
13
47
17
14
14
5
4
80
16
14
50
10
9
5
5
5
17
6
5
14
5
4
−8
−3
−2
150
30
26
175
35
30
150
30
26
150
30
26
60
12
10
100
20
17
65
13
11
5
5
5
190
38
33
220
44
37
190
38
33
190
38
33
75
15
13
t
PHL
/ t
PLH
ns
Fig.8
t
PZH
/ t
PZL
ns
Fig.9
t
PHZ
/ t
PLZ
ns
Fig.9
t
THL
/ t
TLH
ns
Fig.7
t
W
LE pulse width
HIGH
set-up time
D
n
to LE
hold time
D
n
to LE
ns
Fig.8
t
su
ns
Fig.10
t
h
ns
Fig.10
September 1993
5
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参数对比
与74HC373PW相近的元器件有：74HC373D、74HCT373D、74HC373、74HC373DB、74HCT373、74HCT373DB、74HCT373PW。描述及对比如下：
型号 74HC373PW 74HC373D 74HCT373D 74HC373 74HC373DB 74HCT373 74HCT373DB 74HCT373PW
描述 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HCT SERIES, 1-BIT DRIVER, TRUE OUTPUT, CDIP20 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
位数 8 8 8 8 8 8 8 8
功能数量 1 1 1 1 1 1 1 1
端子数量 20 20 20 20 20 20 20 20
输出特性 3-STATE 3-STATE 3-STATE 3-ST 3-STATE 3-ST 3-STATE 3-STATE
表面贴装 YES YES YES Yes YES Yes YES YES
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子位置 DUAL DUAL DUAL 双 DUAL 双 DUAL DUAL
是否Rohs认证 符合 符合 符合 - 符合 - 符合 符合
厂商名称 Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.)
包装说明 TSSOP, TSSOP20,.25 SOP, SOP20,.4 SOP, SOP20,.4 - SSOP, SSOP20,.3 - SSOP, SSOP20,.3 TSSOP, TSSOP20,.25
Reach Compliance Code unknow unknown unknow - unknow - unknow unknow
JESD-30 代码 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 - R-PDSO-G20 - R-PDSO-G20 R-PDSO-G20
负载电容（CL） 50 pF 50 pF 50 pF - 50 pF - 50 pF 50 pF
逻辑集成电路类型 D LATCH D LATCH D LATCH - D LATCH - D LATCH D LATCH
最大I（ol） 0.006 A 0.006 A 0.006 A - 0.006 A - 0.006 A 0.006 A
最高工作温度 125 °C 125 °C 125 °C - 125 °C - 125 °C 125 °C
最低工作温度 -40 °C -40 °C -40 °C - -40 °C - -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SOP SOP - SSOP - SSOP TSSOP
封装等效代码 TSSOP20,.25 SOP20,.4 SOP20,.4 - SSOP20,.3 - SSOP20,.3 TSSOP20,.25
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR - RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE - SMALL OUTLINE, SHRINK PITCH - SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法 TUBE BULK PACK BULK PACK - TUBE - TUBE TUBE
电源 2/6 V 2/6 V 5 V - 2/6 V - 5 V 5 V
Prop。Delay @ Nom-Su 45 ns - 45 ns - 45 ns - 45 ns 45 ns
认证状态 Not Qualified Not Qualified Not Qualified - Not Qualified - Not Qualified Not Qualified
技术 CMOS CMOS CMOS - CMOS - CMOS CMOS
端子节距 0.635 mm 1.27 mm 1.27 mm - 0.635 mm - 0.635 mm 0.635 mm
Base Number Matches 1 - 1 - 1 - 1 1
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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