INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4015
Dual 4-bit serial-in/parallel-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift
register
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
74HC/HCT4015
The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q
0
to
1Q
3
and 2Q
0
to 2Q
3
) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ
0
to nQ
3
to LOW, independent of nCP and nD.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nCP to nQ
n
maximum clock frequency
input capacitance
power dissipation capacitance per register notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V 16
110
3.5
35
HCT
18
74
3.5
40
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
PIN DESCRIPTION
PIN NO.
5, 4, 3, 10
6, 14
7, 15
8
9, 1
13, 12, 11, 2
16
SYMBOL
1Q
0
to 1Q
3
1MR, 2MR
1D, 2D
GND
1CP, 2CP
2Q
0
to 2Q
3
V
CC
NAME AND FUNCTION
flip-flop outputs
asynchronous master reset inputs (active HIGH)
serial data inputs
ground (0 V)
clock inputs (LOW-to-HIGH, edge-triggered)
flip-flop outputs
positive supply voltage
74HC/HCT4015
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
74HC/HCT4015
Fig.5
Fig.4 Functional diagram.
Logic diagram (one 4-bit
serial-in/parallel-out shift register).
FUNCTION TABLE
INPUTS
n
1
2
3
4
nCP
↑
↑
↑
↑
↓
X
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock transition
↓
= HIGH-to-LOW clock transition
n = number of clock pulse transitions
D
n
= either HIGH or LOW
APPLICATIONS
•
Serial-to-parallel converter
•
Buffer stores
•
General purpose register
nD
D
1
D
2
D
3
D
4
X
X
nMR nQ
0
L
L
L
L
L
H
L
L
D
1
D
2
D
3
D
4
OUTPUTS
nQ
1
X
D
1
D
2
D
3
nQ
2
X
X
D
1
D
2
L
nQ
3
X
X
X
D
1
L
no change
December 1990
4
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
n
propagation delay
nMR to nQ
n
output transition time
+25
typ.
52
19
15
44
16
13
19
7
6
80
16
14
80
16
14
60
12
10
60
12
10
5
5
5
6.0
30
35
17
6
5
17
6
5
17
6
5
8
3
2
0
0
0
33
100
119
−40
to
+85
max. min.
175
35
30
175
35
30
75
15
13
100
20
17
100
20
17
75
15
13
75
15
13
5
5
5
4.8
24
28
max.
220
44
37
220
44
37
95
19
16
120
24
20
120
24
20
90
18
15
90
18
15
5
5
5
4.0
20
24
−40
to
+125
min.
max.
265
53
45
265
53
45
110
22
19
74HC/HCT4015
TEST CONDITIONS
UNIT
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
ns
t
PHL
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
master reset pulse
width HIGH
removal time
nMR to nCP
set-up time
nD to nCP
hold time
nD to nCP
maximum clock pulse
frequency
ns
Fig.6
t
W
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.8
t
h
ns
Fig.8
f
max
MHz
Fig.6
December 1990
5
