INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4094
8-stage shift-and-store bus register
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP
0
to QP
7
). The parallel outputs
may be connected directly to common bus lines.
Data is shifted on the positive-going clock (CP) transitions.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4094
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
1
and QS
2
) are available for
cascading a number of “4094” devices. Data is available at
QS
1
on the positive-going clock edges to allow high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS
2
on
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
APPLICATIONS
•
Serial-to-parallel data conversion
•
Remote control holding register
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to QS
1
CP to QS
2
CP to QP
n
STR to QP
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
13
20
18
95
3.5
83
19
18
21
19
86
3.5
92
ns
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7,14, 13, 12, 11
8
9, 10
15
16
SYMBOL
STR
D
CP
QP
0
to QP
7
GND
QS
1
, QS
2
OE
V
CC
NAME AND FUNCTION
strobe input
serial input
clock input
parallel outputs
ground (0 V)
serial outputs
output enable input
positive supply voltage
74HC/HCT4094
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74HC/HCT4094
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
FUNCTION TABLE
INPUTS
CP
↑
↓
↑
↑
↑
↓
Notes
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
PARALLEL OUTPUTS
QP
0
Z
Z
NC
L
H
NC
QP
n
Z
Z
NC
QP
n - 1
QP
n - 1
NC
74HC/HCT4094
SERIAL
OUTPUTS
QS
1
Q’
6
NC
Q’
6
Q’
6
Q’
6
NC
QS
2
NC
QP
7
NC
NC
NC
QP
7
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
NC= no change
↑
= LOW-to-HIGH CP transition
↓
= HIGH-to-LOW CP transition
Q’
6
= the information in the seventh register stage is transferred to the 8th register stage and QS
n
output at the
positive clock edge
Fig.6 Timing diagram.
December 1990
5
