74HC75
Quad bistable transparant latch
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC
standard no. 7A.
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched
outputs remain stable as long as the LEnn is LOW.
2. Features
s
s
s
s
s
Complementary Q and Q outputs
V
CC
and GND on the center pins
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
Philips Semiconductors
74HC75
Quad bistable transparant latch
3. Quick reference data
Table 1:
Symbol
t
PHL
, t
PLH
Quick reference data
Parameter
propagation delay
nD to nQ, nQ
LEnn to nQ, nQ
C
I
C
PD
[1]
Conditions
C
L
= 15 pF;
V
CC
= 5 V
Min
Typ
Max
Unit
-
-
-
V
I
= GND to V
CC
[1]
11
11
3.5
42
-
-
-
-
ns
ns
pF
pF
input capacitance
power dissipation
capacitance per latch
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC75N
74HC75D
74HC75DB
74HC75PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Type number
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 20
Philips Semiconductors
74HC75
Quad bistable transparant latch
5. Functional diagram
2
1D
D
Q
1Q
16
13
LE12
CP
L1
1Q
1
3
2D
D
Q
2Q
13
15
2
1D
LE12
1Q
1Q
2Q
2Q
L1,2
L3,4
16
1
15
14
CP
L2
2Q
14
3
2D
6
3D
D
Q
3Q
10
6
3D
3Q
3Q
4Q
4Q
LE34
4
10
11
9
8
4
LE34
CP
L3
3Q
11
7
4D
001aab851
7
4D
D
Q
4Q
9
CP
L4
4Q
8
001aab853
Fig 1. Functional diagram
Fig 2. Logic symbol
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 20
Philips Semiconductors
74HC75
Quad bistable transparant latch
1D
D
Q
1Q
LE12
CP
LATCH
1
1Q
13
C1
16
2
1D
2D
D
Q
2Q
1
15
CP
LATCH
2
2Q
3
14
4
C1
9
3D
D
Q
3Q
7
1D
8
10
LE34
CP
LATCH
3
3Q
6
11
001aab852
4D
D
Q
4Q
CP
LATCH
4
4Q
001aab854
Fig 3. IEC logic symbol
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
1Q
1D
2D
LE34
V
CC
3D
4D
4Q
1
2
3
4
16 1Q
15 2Q
14 2Q
13 LE12
75
5
6
7
8
001aab850
12 GND
11 3Q
10 3Q
9
4Q
Fig 5. Pin configuration
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
4 of 20
Philips Semiconductors
74HC75
Quad bistable transparant latch
6.2 Pin description
Table 3:
Symbol
1Q
1D
2D
LE34
V
CC
3D
4D
4Q
4Q
3Q
3Q
GND
LE12
2Q
2Q
1Q
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
complementary latch output 1
data input 1
data input 2
latch enable input for latches 3 and 4 (active HIGH)
positive supply voltage
data input 3
data input 4
complementary latch output 4
latch output 4
latch output 3
complementary latch output 3
ground (0 V)
latch enable input for latches 1 and 2 (active HIGH)
complementary latch output 2
latch output 2
latch output 1
7. Functional description
7.1 Function table
Table 4:
Function table
[1]
Input
LEnn
Data enabled
Data latched
[1]
Operating mode
Output
nD
L
H
X
nQ
L
H
q
nQ
H
L
q
H
H
L
H = HIGH voltage level;
L = LOW voltage level;
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW
LEnn transition;
X = don’t care.
9397 750 13816
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
5 of 20
