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74HCT259PW-T

Latches 8-BIT ADDRSSBL LATCH

器件类别：逻辑    逻辑   

厂商名称：NXP(恩智浦)

厂商官网：https://www.nxp.com

器件标准：

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器件参数
参数名称
属性值
Source Url Status Check Date
2013-06-14 00:00:00
是否Rohs认证
符合
厂商名称
NXP(恩智浦)
零件包装代码
TSSOP
包装说明
4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
针数
16
Reach Compliance Code
unknown
其他特性
1:8 DMUX FOLLOWED BY LATCH
系列
HCT
JESD-30 代码
R-PDSO-G16
JESD-609代码
e4
长度
5 mm
负载电容（CL）
50 pF
逻辑集成电路类型
D LATCH
最大I（ol）
0.00002 A
湿度敏感等级
1
位数
1
功能数量
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-40 °C
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP16,.25
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法
TAPE AND REEL
峰值回流温度（摄氏度）
260
电源
5 V
Prop。Delay @ Nom-Sup
59 ns
传播延迟（tpd）
57 ns
认证状态
Not Qualified
座面最大高度
1.1 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
触发器类型
LOW LEVEL
宽度
4.4 mm
Base Number Matches
1
文档预览
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT259
8-bit addressable latch
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit addressable latch
FEATURES
•
Combines demultiplexer and 8-bit latch
•
Serial-to-parallel capability
•
Output from each storage bit available
•
Random (addressable) data entry
•
Easily expandable
•
Common reset input
•
Useful as a 3-to-8 active HIGH decoder
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT259 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The “259” are multifunctional devices
74HC/HCT259
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q
0
to Q
7
), functions are available.
The “259” also incorporates an active LOW common reset
(MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The “259” has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the D input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address (A
0
to A
2
)
and data (D) input. When operating the “259” as an
addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this
should only be done while in the memory mode. The mode
select table summarizes the operations of the “259”.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
D to Q
n
A
n
, LE to Q
n
t
PHL
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
MR to Q
n
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
18
17
15
3.5
19
20
20
20
3.5
19
ns
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-bit addressable latch
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
1, 2, 3
4, 5, 6, 7, 9 10, 11, 12
8
13
14
15
16
SYMBOL
A
0
to A
2
Q
0
to Q
7
GND
D
LE
MR
V
CC
NAME AND FUNCTION
address inputs
latch outputs
ground (0 V)
data input
latch enable input (active LOW)
conditional reset input (active LOW)
positive supply voltage
74HC/HCT259
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
Fig.4 Functional diagram.
MODE SELECT TABLE
LE
L
H
L
H
MR
H
H
L
L
MODE
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
December 1990
4
Philips Semiconductors
Product specification
8-bit addressable latch
FUNCTION TABLE
OPERATING
MODES
master reset
INPUTS
MR
L
L
L
L
L
L
L
L
L
H
H
H
H
H
addressable latch
H
H
H
H
Notes
L
L
L
L
d
d
d
d
L
H
L
H
L
L
H
H
H
H
H
H
q
0
q
0
q
0
q
0
q
1
q
1
q
1
q
1
q
2
q
2
q
2
q
2
q
3
q
3
q
3
q
3
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
X
d
d
d
d
d
d
d
d
X
d
d
d
d
D
A
0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
A
1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
A
2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
L
Q=d
L
L
L
L
L
L
L
q
0
Q=d
q
0
q
0
q
0
Q
0
L
L
Q=d
L
L
L
L
L
L
q
1
q
1
Q=d
q
1
q
1
Q
1
L
L
L
Q=d
L
L
L
L
L
q
2
q
2
q
2
Q=d
q
2
Q
2
L
L
L
L
Q=d
L
L
L
L
q
3
q
3
q
3
q
3
Q=d
74HC/HCT259
OUTPUTS
Q
3
L
L
L
L
L
Q=d
L
L
L
q
4
q
4
q
4
q
4
q
4
Q=d
q
4
q
4
q
4
Q
4
L
L
L
L
L
L
Q=d
L
L
q
5
q
5
q
5
q
5
q
5
q
5
Q=d
q
5
q
5
Q
5
L
L
L
L
L
L
L
Q=d
L
q
6
q
6
q
6
q
6
q
6
q
6
q
6
Q=d
q
6
Q
6
L
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
Q
7
demultiplex
(active HIGH)
decoder
(when D = H)
store (do nothing)
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared
December 1990
5
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参数对比
与74HCT259PW-T相近的元器件有：74HCT259D、74HCT259DB、74HC259DB-T、74HCT259DB-T。描述及对比如下：
型号 74HCT259PW-T 74HCT259D 74HCT259DB 74HC259DB-T 74HCT259DB-T
描述 Latches 8-BIT ADDRSSBL LATCH Latches 8-BIT ADDRSSBL LATCH Latches 8-BIT ADDRSSBL LATCH Latches 8-BIT ADDRSSBL LATCH Latches 8-BIT ADDRSSBL LATCH
是否Rohs认证 符合 符合 符合 符合 符合
厂商名称 NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
零件包装代码 TSSOP SOIC SSOP SSOP SSOP
包装说明 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 3.90 MM, PLASTIC, MS-012, SOT-109, SOP-16 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16 SSOP, 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16
针数 16 16 16 16 16
Reach Compliance Code unknown unknown unknown unknown unknown
其他特性 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH
系列 HCT HCT HCT HC/UH HCT
JESD-30 代码 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609代码 e4 e4 e4 e4 e4
长度 5 mm 9.9 mm 6.2 mm 6.2 mm 6.2 mm
逻辑集成电路类型 D LATCH D LATCH D LATCH D LATCH D LATCH
湿度敏感等级 1 1 1 1 1
位数 1 1 1 1 1
功能数量 1 1 1 1 1
端子数量 16 16 16 16 16
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C
输出极性 TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SOP SSOP SSOP SSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度） 260 260 260 260 260
传播延迟（tpd） 57 ns 57 ns 57 ns 255 ns 57 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.1 mm 1.75 mm 2 mm 2 mm 2 mm
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 6 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 2 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.65 mm 1.27 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30 30 30
触发器类型 LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL
宽度 4.4 mm 3.9 mm 5.3 mm 5.3 mm 5.3 mm
Base Number Matches 1 1 1 1 1
Source Url Status Check Date 2013-06-14 00:00:00 - - 2013-06-14 00:00:00 2013-06-14 00:00:00
负载电容（CL） 50 pF 50 pF 50 pF - -
最大I（ol） 0.00002 A 0.004 A 0.004 A - -
封装等效代码 TSSOP16,.25 SOP16,.25 SSOP16,.3 - -
电源 5 V 5 V 5 V - -
Prop。Delay @ Nom-Sup 59 ns 59 ns 59 ns - -
最小 fmax - 60 MHz 60 MHz - 60 MHz
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器件捷径:
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