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74HC4066-Q100;
74HCT4066-Q100
Quad single-pole single-throw analog switch
Rev. 3 — 16 December 2013
Product data sheet
1. General description
The 74HC4066-Q100; 74HCT4066-Q100 is a quad single pole, single throw analog
switch. Each switch features two input/output terminals (nY and nZ) and an active HIGH
enable input (nE). When nE is LOW, the analog switch is turned off. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels nE inputs:
For 74HC4066-Q100: CMOS level
For 74HCT4066-Q100: TTL level
Low ON resistance:
50
(typical) at V
CC
= 4.5 V
45
(typical) at V
CC
= 6.0 V
35
(typical) at V
CC
= 9.0 V
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC4066-Q100; 74HCT4066-Q100
Quad single-pole single-throw analog switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC4066D-Q100
74HCT4066D-Q100
74HC4066PW-Q100
74HCT4066PW-Q100
74HC4066BQ-Q100
74HCT4066BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1
13
4
5
8
6
11
12
1Y
1E
1Z
2
1
13 #
1
2
4
5#
3
8
9
6#
11
12 #
(a)
1
X1
1
X1
1
X1
1
X1
(b)
1
2
2Y
2E
3Y
3E
4Y
4E
2Z
3
13 #
4
5#
1
3
3Z
9
8
6#
11
1
9
10
4Z
1
10
10
12 #
001aad269
001aad270
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
nY
nE
V
CC
V
CC
GND
nZ
001aad271
Fig 3.
Schematic diagram (one switch)
74HC_HCT4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2013
2 of 23
NXP Semiconductors
74HC4066-Q100; 74HCT4066-Q100
Quad single-pole single-throw analog switch
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 4.
Pin configuration for SO14 and TSSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Z, 2Z, 3Z, 4Z
1Y, 2Y, 3Y, 4Y
GND
1E, 2E, 3E, 4E
V
CC
Pin description
Pin
2, 3, 9, 10
1, 4, 8, 11
7
13, 5, 6, 12
14
Description
independent input or output
independent input or output
ground (0 V)
enable input (active HIGH)
supply voltage
74HC_HCT4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2013
3 of 23
NXP Semiconductors
74HC4066-Q100; 74HCT4066-Q100
Quad single-pole single-throw analog switch
6. Functional description
Table 3.
Input nE
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Switch
OFF
ON
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
V
SW
=
0.5
V to V
CC
+ 0.5 V
[1]
Min
0.5
-
-
-
-
-
65
Max
+11.0
20
20
25
50
50
+150
-
100
Unit
V
mA
mA
mA
mA
mA
C
500
mW
T
amb
=
40 C
to +125
C
per switch
[2]
-
To avoid drawing V
CC
current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed V
CC
or GND.
For SO14 packages: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
[2]
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
74HC4066-Q100
Min
V
CC
V
I
V
SW
T
amb
t/V
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 10.0 V
2.0
GND
GND
40
-
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
-
Max
10.0
V
CC
V
CC
+125
625
139
83
35
74HCT4066-Q100
Min
4.5
GND
GND
40
-
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
-
Max
5.5
V
CC
V
CC
+125
-
139
-
-
V
V
V
C
ns/V
ns/V
ns/V
ns/V
Unit
Symbol Parameter
74HC_HCT4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 16 December 2013
4 of 23
