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74LCX16240MTDX_NL

Bus Driver, LVC/LCX/Z Series, 4-Func, 4-Bit, Inverted Output, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48

器件类别:逻辑    逻辑   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Fairchild
零件包装代码
TSSOP
包装说明
TSSOP, TSSOP48,.3,20
针数
48
Reach Compliance Code
compliant
控制类型
ENABLE LOW
系列
LVC/LCX/Z
JESD-30 代码
R-PDSO-G48
JESD-609代码
e3
长度
12.5 mm
负载电容(CL)
50 pF
逻辑集成电路类型
BUS DRIVER
最大I(ol)
0.024 A
湿度敏感等级
2
位数
4
功能数量
4
端口数量
2
端子数量
48
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP48,.3,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法
TAPE AND REEL
峰值回流温度(摄氏度)
260
电源
3.3 V
Prop。Delay @ Nom-Sup
4.5 ns
传播延迟(tpd)
5.4 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
2 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Matte Tin (Sn)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
6.1 mm
Base Number Matches
1
文档预览
74LCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs and Outputs
February 1994
Revised May 2005
74LCX16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
The LCX16240 contains sixteen inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmit-
ter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The LCX16240 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capacity of interfacing to a 5V signal
environment.
The LCX16240 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V to 3.6V V
CC
specifications provided
s
4.5 ns t
PD
max (V
CC
3.3V), 20
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
r
24 mA output drive (V
CC
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX16240MEA
74LCX16240MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
GTO
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS011999
www.fairchildsemi.com
74LCX16240
Truth Tables
Inputs
OE
1
L
L
H
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
H
L
Z
OE
3
L
L
H
Inputs
I
8
–I
11
L
H
Z
Outputs
O
8
–O
11
H
L
Z
Inputs
OE
2
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
I
4
–I
7
L
H
X
O
4
–O
7
H
L
Z
OE
4
L
L
H
Inputs
I
12
–I
15
L
H
Z
Outputs
O
12
–O
15
H
L
Z
Functional Description
The LCX16240 contains sixteen inverting buffers with
3-STATE standard outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but inde-
pendent of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input for
each nibble. When OE
n
is LOW, the outputs are in 2-state
mode. When OE
n
is HIGH, the outputs are in the high
impedance mode, but this does not interfere with entering
new data into the inputs.
Logic Diagram
www.fairchildsemi.com
2
74LCX16240
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I

GND
V
O

GND
V
O
!
V
CC
V
mA
mA
mA
mA
mA

0.5 to

7.0

0.5 to

7.0

0.5 to

7.0

0.5 to V
CC

0.5

50

50

50
r
50
r
100
r
100

65 to

150
q
C
Recommended Operating Conditions
(Note 4)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
V
CC
V
CC
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
3.0V

3.6V
2.7V

3.0V
2.3V

2.7V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
r
24
r
12
r
8

40
0
85
10
mA
q
C
ns/V
'
t/
'
V
Note 2:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
Conditions
V
CC
(V)
2.3

2.7
2.7

3.6
2.3

2.7
2.7

3.6
T
A

40
q
C to

85
q
C
Max
Min
1.7
2.0
Units
V
0.7
0.8
V
CC

0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
V

100
P
A

8 mA

12 mA

18 mA

24 mA
100
P
A
8 mA
12 mA
16 mA
24 mA
2.3

3.6
2.3
2.7
3.0
3.0
2.3

3.6
2.3
2.7
3.0
3.0
2.3

3.6
2.3

3.6
0
V
V
0
d
V
I
d
5.5V
0
d
V
O
d
5.5V
V
I
V
IH
or V
IL
5.5V
V
I
or V
O
r
5.0
r
5.0
10
P
A
P
A
P
A
3
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74LCX16240
DC Electrical Characteristics
Symbol
I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
V
I
V
IH
(Continued)
V
CC
(V)
V
CC
or GND
V
CC

0.6V
2.3

3.6
2.3

3.6
2.3

3.6
T
A
Conditions

40
q
C to

85
q
C
Max
20
Units
Min
3.6V
d
V
I
, V
O
d
5.5V (Note 5)
r
20
500
P
A
P
A
'
I
CC
Note 5:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
C
L
Min
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSHL
t
OSLH
Output to Output Skew (Note 6)
Output Disable Time
Propagation Delay
Data to Output
Output Enable Time
1.0
1.0
1.0
1.0
1.0
1.0
3.3V
r
0.3V
50 pF
Max
4.5
4.5
5.4
5.4
5.3
5.3
1.0
1.0

40
q
C to

85
q
C, R
L
V
CC
C
L
Min
1.0
1.0
1.0
1.0
1.0
1.0
2.7V
50 pF
Max
5.3
5.3
6.0
6.0
5.4
5.4
500
:
V
CC
C
L
Min
1.0
1.0
1.0
1.0
1.0
1.0
2.5
r
0.2V
30 pF
Max
5.4
5.4
7.0
7.0
6.4
6.4
ns
ns
ns
ns
Units
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
C
L
C
L
C
L
C
L
50 pF, V
IH
30pF, V
IH
50 pF, V
IH
30pF, V
IH
Conditions
3.3V, V
IL
2.5V, V
IL
3.3V, V
IL
2.5V, V
IL
0V
0V
0V
0V
V
CC
(V)
3.3
2.5
3.3
2.5
T
A
25
q
C
0.8
0.6
Typical
Unit
V
V

0.8

0.6
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
CC
V
CC
Open, V
I
3.3V, V
I
3.3V, V
I
Conditions
0V or V
CC
0V or V
CC
0V or V
CC
, f
10 MHz
Typical
7
8
20
Units
pF
pF
pF
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4
74LCX16240
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Test
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
,t
PHZ
Switch
Open
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and t
rec
Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
r
= t
f
= 3ns)
Symbol
V
mi
V
mo
V
x
V
y
V
CC
3.3V
r
0.3V
1.5V
1.5V
V
OL

0.3V
V
OH

0.3V
2.7V
1.5V
1.5V
V
OL

0.3V
V
OH

0.3V
t
rise
and t
fall
2.5V
r
0.2V
V
CC
/2
V
CC
/2
V
OL

0.15V
V
OH

0.15V
5
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