74LVC1G00
Single 2-input NAND gate
Rev. 10 — 2 July 2012
Product data sheet
1. General description
The 74LVC1G00 provides the single 2-input NAND function.
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC1G00
Single 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G00GW
74LVC1G00GV
74LVC1G00GM
74LVC1G00GF
74LVC1G00GN
74LVC1G00GS
74LVC1G00GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP5
SC-74A
XSON6
XSON6
XSON6
XSON6
X2SON5
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1
0.5 mm
Version
SOT353-1
SOT753
SOT886
SOT891
Type number
extremely thin small outline package; no leads; SOT1115
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads; SOT1202
6 terminals; body 1.0
1.0
0.35 mm
X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8
0.8
0.35 mm
SOT1226
4. Marking
Table 2.
Marking codes
Marking
[1]
VA
V00
VA
VA
VA
VA
VA
Type number
74LVC1G00GW
74LVC1G00GV
74LVC1G00GM
74LVC1G00GF
74LVC1G00GN
74LVC1G00GS
74LVC1G00GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
B
A
1
Y
4
2
A
mna097
mna098
&
4
Y
mna099
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74LVC1G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 2 July 2012
2 of 19
NXP Semiconductors
74LVC1G00
Single 2-input NAND gate
6. Pinning information
6.1 Pinning
74LVC1G00
74LVC1G00
B
A
1
2
GND
GND
3
001aab608
B
5
V
CC
1
6
V
CC
A
2
5
n.c.
3
4
Y
4
Y
001aab603
Transparent top view
Fig 4.
Pin configuration SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
74LVC1G00
74LVC1G00
B
1
3
GND
A
2
4
aaa-003018
5
V
CC
B
A
GND
1
2
3
6
5
4
V
CC
n.c.
Y
Y
001aaf051
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7.
Pin configuration SOT1226 (X2SON5)
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
n.c.
V
CC
Pin description
Pin
TSSOP5 and X2SON5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
data input
data input
ground (0 V)
data output
not connected
supply voltage
Description
74LVC1G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 2 July 2012
3 of 19
NXP Semiconductors
74LVC1G00
Single 2-input NAND gate
7. Functional description
Table 4.
Inputs
A
L
L
H
H
[1]
Function table
[1]
Outputs
B
L
H
L
H
Y
H
H
H
L
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
+100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
74LVC1G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 2 July 2012
4 of 19
NXP Semiconductors
74LVC1G00
Single 2-input NAND gate
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
V
CC
= 0 V; Power-down mode
Conditions
Min
1.65
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
40 C
to +85
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.1
0.45
0.3
0.4
0.55
0.55
5
40 C
to +125
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
Max
-
-
-
-
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.1
0.70
0.45
0.60
0.80
0.80
100
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
Unit
0.35V
CC
V
74LVC1G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 2 July 2012
5 of 19
电源技术
