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74LVC573A

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 5 — 19 February 2013

Product data sheet

1. General description

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type

inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch

Enable (LE) input and an Output Enable (OE) input are common to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches

are transparent, that is, a latch output changes each time its corresponding D-input

changes. When LE is LOW, the latches store the information that was present at the

D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE

is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does

not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V or 5 V applications.

The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin

arrangement.

2. Features and benefits



5 V tolerant inputs/outputs, for interfacing with 5 V logic

Supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

High-impedance when V

= 0 V

Flow-through pinout architecture

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

NXP Semiconductors

74LVC573A

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LVC573AD

74LVC573ADB

40 C

to +125

C

40 C

to +125

C

Name

SO20

SSOP20

TSSOP20

Description

plastic small outline package; 20 leads;

body width 7.5 mm

plastic shrink small outline package; 20 leads;

body width 5.3 mm

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

Version

SOT163-1

SOT339-1

SOT360-1

SOT764-1

Type number

74LVC573APW

40 C

to +125

C

74LVC573ABQ

40 C

to +125

C

DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 20 terminals;

body 2.5



4.5



0.85 mm

DHXQFN20 plastic dual in-line compatible thermal enhanced

extremely thin quad flat package; no leads; 20

terminals; body 4.5



2.5



0.5 mm

74LVC573ABX

40 C

to +125

C

SOT1045-2

4. Functional diagram

mna807

EN1

mna808

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

74LVC573A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 19 February 2013

2 of 20

NXP Semiconductors

74LVC573A

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

LATCH

1 to 8

3-STATE

OUTPUTS

Q0 19

Q1 18

Q2 17

Q3 16

Q4 15

Q5 14

Q6 13

Q7 12

11 LE

1 OE

mna809

Fig 3.

Functional diagram

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

LATCH

LE LE

mna810

Fig 4.

Logic diagram

74LVC573A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 19 February 2013

3 of 20

NXP Semiconductors

74LVC573A

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

5. Pinning information

5.1 Pinning

terminal 1

index area

20 V

19 Q0

18 Q1

17 Q2

16 Q3

15 Q4

14 Q5

13 Q6

12 Q7

11 LE

001aad099

20 V

19 Q0

18 Q1

17 Q2

16 Q3

15 Q4

14 Q5

13 Q6

12 Q7

LE 11

GND 10

GND

(1)

573

GND 10

001aad100

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5.

Pin configuration for SO20 and (T)SSOP20

Fig 6.

Pin configuration for DHVQFN20 and

DHXQFN20

5.2 Pin description

Table 2.

Symbol

D[0:7]

Q[0:7]

GND

Pin description

2, 3, 4, 5, 6, 7, 8, 9

19, 18, 17, 16, 15, 14, 13, 12

Description

output enable input (active LOW)

latch enable input (active HIGH)

data input

data output

ground (0 V)

supply voltage

74LVC573A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 19 February 2013

4 of 20