74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 03 — 11 May 2004
Product data sheet
1. General description
The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an
output enable input (pin OE) are common to all flip-flops. The ten flip-flops will store the
state of their individual D-inputs that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops is
available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE inputs does not affect the state of the flip-flops.
2. Features
s
s
s
s
s
s
s
s
s
s
5 V tolerant inputs and outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
10-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard JESD8-B
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
f
max
C
I
C
PD
Parameter
propagation delay CP to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V
outputs enabled
outputs disabled
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
[1] [2]
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
Min
-
-
-
-
-
-
-
Typ
3.7
3.5
3.0
200
5.0
17
11
Max
-
-
-
-
-
-
-
Unit
ns
ns
ns
MHz
pF
pF
pF
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74LVC821AD
74LVC821ADB
74LVC821APW
74LVC821ABQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO24
SSOP24
TSSOP24
Description
Version
plastic small outline package; 24 leads; body width SOT137-1
7.5 mm
plastic shrink small outline package; 24 leads; body SOT340-1
width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
Type number
DHVQFN24 plastic dual in-line compatible thermal enhanced
SOT815-1
very thin quad flat package; no leads; 24 terminals;
body 3.5
×
5.5
×
0.85 mm
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
2 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
5. Functional diagram
2
3
4
5
6
7
8
9
10
11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
FF0
to
FF9
3-STATE
OUTPUTS
Q0 23
Q1 22
Q2 21
Q3 20
Q4 19
Q5 18
Q6 17
Q7 16
Q8 15
Q9 14
13 CP
1 OE
001aaa679
Fig 1. Functional diagram.
13
13
2
3
4
5
6
7
8
9
10
11
CP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE
1
001aaa677
C1
EN
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
1D
23
22
21
20
19
18
17
16
15
14
001aaa678
Fig 2. Logic symbol.
Fig 3. IEC logic symbol.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
3 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
D0
D1
D2
D3
D4
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
CP
OE
Q0
Q1
Q2
Q3
Q4
D5
D6
D7
D8
D9
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF6
FF7
FF8
FF9
FF10
Q5
Q6
Q7
Q8
Q9
001aaa681
Fig 4. Logic diagram.
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
4 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
6. Pinning information
6.1 Pinning
OE
1
D0
D1
2
3
4
5
6
V
CC
24
23
22
21
20
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
D3
D4
D5
D6
D7
D8
D9
D2
821A
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
GND
(1)
7
8
9
10
11
12
Top view
GND
13
CP
001aaa680
18
17
16
15
14
D8 10
D9 11
GND 12
001aaa676
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO24 and (T)SSOP24.
Fig 6. Pin configuration DHVQFN24.
6.2 Pin description
Table 3:
Symbol
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
Description
output enable input (active LOW)
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
9397 750 13276
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 May 2004
5 of 20
