74LVT14
3.3 V hex inverter Schmitt trigger
Rev. 02 — 25 April 2008
Product data sheet
1. General description
The 74LVT14 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
It is capable of transforming slowly changing input signals into sharply defined, jitter free
output signals. In addition, it has a greater noise margin than conventional inverters.
Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase
splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to
effectively speed-up slow input transitions, and provide different input threshold voltages
for positive-going and negative-going inputs. The threshold differential (typically 600 mV)
is determined internally by resistor ratios and is insensitive to temperature and supply
voltage variations.
2. Features
I
I
I
I
I
I
I
Different positive and negative going input threshold voltages
Tolerant of slow input transitions
High noise immunity
TTL input and output switching levels
Output capability: +32 mA/−20 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT14D
74LVT14DB
74LVT14PW
74LVT14BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 7.5 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
4.5
×
0.85 mm
NXP Semiconductors
74LVT14
3.3 V hex inverter Schmitt trigger
4. Functional diagram
1
2
3
1
1A
1Y
2
5
4
4
3
2A
2Y
6
5
3A
3Y
6
9
8
9
4A
4Y
8
11
10
11
5A
5Y
10
13
12
13
6A
6Y
12
A
Y
mna025
mna204
001aac497
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LVT14
terminal 1
index area
14 V
CC
13 6A
12 6Y
11 5A
GND
(1)
7
8
10 5Y
9
GND
4Y
4A
1A
2
3
4
5
6
1
1Y
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
001aah920
74LVT14
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
2A
2Y
3A
3Y
4A
4Y
001aah921
Transparent top view
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
74LVT14_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 25 April 2008
2 of 13
NXP Semiconductors
74LVT14
3.3 V hex inverter Schmitt trigger
5.2 Pin description
Table 2.
Symbol
1A to 6A
1Y to 6Y
GND
V
CC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
positive supply voltage
6. Functional description
Table 3.
Inputs
nA
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function selection
Output
nY
H
L
7. Limiting values
Table 4.
Limiting values
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[2]
Min
−0.5
−0.5
−0.5
−50
−50
-
−32
−65
Max
+4.6
+7.0
+7.0
-
-
64
-
+150
+150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
output in OFF or HIGH state
V
I
< 0 V
V
O
< 0 V
output in LOW state
output in HIGH state
[2]
T
amb
=
−40 °C
to +85
°C
[3]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
74LVT14_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 25 April 2008
3 of 13
NXP Semiconductors
74LVT14
3.3 V hex inverter Schmitt trigger
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
I
OH
I
OL
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
LOW-level output current
ambient temperature
input transition rise and fall rate
in free air
output enabled
Conditions
Min
2.7
0
−20
-
−40
0
Typ
-
-
-
-
-
-
Max
3.6
5.5
-
32
+85
10
Unit
V
V
mA
mA
°C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
T+
V
T−
V
H
V
IK
V
IH
V
IL
V
OH
positive-going threshold voltage
hysteresis voltage
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
V
CC
= 2.7 V to 3.6 V; I
OH
=
−100 µA
V
CC
= 2.7 V; I
OH
=
−6
mA
V
CC
= 3.0 V; I
OH
=
−20
mA
V
OL
LOW-level output voltage
V
CC
= 2.7 V; I
OL
= 100
µA
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V; I
OL
= 32 mA
I
I
I
OFF
I
CC
input leakage current
power-off leakage current
supply current
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
V
CC
= 3.6 V; V
I
= V
CC
or GND
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
V
CC
= 3.6 V; V
I
= GND or V
CC
; I
O
= 0 A
outputs HIGH
outputs LOW
∆I
CC
additional supply current
per input pin; V
CC
= 3.0 V to 3.6 V;
one input = V
CC
−
0.6 V
other inputs at V
CC
or GND
V
I
= 0 V or 3.0 V
[2]
Conditions
V
CC
= 3.3 V; see
Figure 7
V
CC
= 3.3 V; see
Figure 7
V
CC
= 2.7 V; I
IK
= –18 mA
1.5
0.9
0.4
−1.2
2.0
-
2.4
2.0
-
-
-
-
-
-
-
-
-
−40 °C
to +85
°C
Min
Typ
[1]
1.7
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
Max
2.0
1.3
-
-
-
0.8
-
-
-
0.2
0.5
0.5
10
±1
±100
0.02
3
0.2
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
negative-going threshold voltage V
CC
= 3.3 V; see
Figure 7
V
CC
−
0.2 -
C
I
[1]
[2]
input capacitance
-
3
-
pF
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
°C.
This is the increase in the supply current for each input at the specified voltage level other than V
CC
or GND.
74LVT14_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 25 April 2008
4 of 13
NXP Semiconductors
74LVT14
3.3 V hex inverter Schmitt trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 8.
Symbol Parameter
t
PLH
LOW to HIGH propagation delay
Conditions
nA to nY
V
CC
= 2.7 V
V
CC
= 3.3 V + 0.3 V
t
PHL
HIGH to LOW propagation delay
nA to nY
V
CC
= 2.7 V
V
CC
= 3.3 V + 0.3 V
[1]
Typical values are measured at T
amb
= 25
°C
and V
CC
= 3.3 V.
−40 °C
to +85
°C
Min
-
1.0
-
1.0
Typ
[1]
-
3.8
-
3.2
Max
6.9
5.7
4.1
4.5
Unit
ns
ns
ns
ns
11. Waveforms
V
I
nA input
GND
t
PHL
V
OH
nY output
V
OL
V
M
V
M
mna344
V
M
V
M
t
PLH
See
Table 8
for measurement points.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6.
nA Input to nY output propagation delays
V
O
V
T+
V
I
V
T−
V
H
V
H
V
T−
V
T+
V
I
mna207
V
O
mna208
a. Transfer characteristics
Fig 7.
Definition of V
T+
, V
T−
and V
H
b. Voltage levels
74LVT14_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 25 April 2008
5 of 13
微控制器 MCU
