74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
Rev. 10 — 1 March 2012
Product data sheet
1. General description
The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (nOE) for easy
cascading and a direction input (nDIR) for direction control.
2. Features and benefits
16-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and
32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVT16245BDL
74LVTH16245BDL
74LVT16245BDGG
74LVTH16245BDGG
74LVT16245BEV
74LVT16245BBX
74LVTH16245BBX
40 C
to +85
C
40 C
to +125
C
VFBGA56
HXQFN60
40 C
to +85
C
TSSOP48
40 C
to +85
C
Name
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
Version
SOT370-1
Type number
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5
7
0.65 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
SOT1134-2
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Fig 1.
Logic symbol
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 1 March 2012
2 of 19
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
1OE
1DIR
48
1
25
2OE
24
2DIR
G3
3EN1 [BA]
3EN2 [AB]
G6
6EN4 [BA]
6EN5 [AB]
1
2
2
3
5
6
8
9
11
12
4
5
13
14
16
17
19
20
22
23
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mna709
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Fig 2. IEC logic symbol
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 1 March 2012
3 of 19
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVT16245B
74LVTH16245B
1DIR
1B0
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 V
CC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aae474
74LVT16245B
1
A
1DIR
2
n.c.
3
n.c.
4
n.c.
5
n.c.
6
1OE
B
1B1
1B0
GND
GND
1A0
1A1
C
1B3
1B2
V
CC
GND
V
CC
GND
1A2
1A3
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
V
CC
18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
001aae471
D
1B5
1B4
1A4
1A5
E
1B7
1B6
1A6
1A7
F
2B0
2B1
2A1
2A0
G
2B2
2B3
GND
GND
2A3
2A2
H
2B4
2B5
V
CC
GND
V
CC
GND
2A5
2A4
J
2B6
2B7
2A7
2A6
K
2DIR
n.c.
n.c.
n.c.
n.c.
2OE
Transparent top view
Fig 3. Pin configuration for SSOP48 and TSSOP48
Fig 4. Pin configuration for VFBGA56
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 1 March 2012
4 of 19
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B13
B15
B16
B17
A25
A24
A23
A22
74LVT16245B
74LVTH16245B
B14
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj656
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5.
Pin configuration SOT1134-2 (HXQFN60)
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 1 March 2012
5 of 19
嵌入式系统
