74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
February 2008
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
■
Input voltage level translation from 5V to 3V
■
Ideal for low power/low noise 3.3V applications
■
Guaranteed simultaneous switching noise level and
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
■
LOW input to S
D
(Set) sets Q to HIGH level
■
LOW input to C
D
(Clear) sets Q to LOW level
■
Clear and Set are independent of clock
■
Simultaneous LOW on C
D
and S
D
makes both Q and
dynamic threshold performance
Q HIGH
Ordering Information
Order
Number
74LVX74M
74LVX74SJ
74LVX74MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
Truth Table
(Each Half)
Inputs
S
D
L
H
L
H
H
H
Outputs
D
X
X
X
H
L
L
X
C
D
H
L
L
H
H
H
CP
X
X
X
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
=
Previous Q(Q) before LOW-to-HIGH Transition
of Clock
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
2
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
V
I
I
OK
Supply Voltage
Parameter
DC Input Diode Current, V
I
=
–0.5V
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
Rating
–0.5V to +7.0V
–20mA
–0.5V to 7V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±25mA
±50mA
–65°C to +150°C
180mW
V
O
I
O
DC Output Voltage
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current
T
STG
Storage Temperature
P
Power Dissipation
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
Parameter
Rating
2.0V to 3.6V
0V to 5.5V
0V to V
CC
–40°C to +85°C
0ns/V to 100ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
3
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
DC Electrical Characteristics
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to
+85°C
Min.
1.5
2.0
2.4
Parameter
HIGH Level Input
Voltage
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
Conditions
Min.
1.5
2.0
2.4
Typ. Max.
Max.
Units
V
V
IL
LOW Level Input
Voltage
0.5
0.8
0.8
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–4mA
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±0.1
2.0
2.0
3.0
1.9
2.9
2.48
0.5
0.8
0.8
V
V
OH
HIGH Level Output
Voltage
V
V
OL
LOW Level Output
Voltage
2.0
3.0
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
4mA
0.1
0.1
0.44
±1.0
20.0
V
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
3.6
3.6
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
µA
µA
Noise Characteristics
(2)
T
A
=
25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
3.3
3.3
3.3
3.3
C
L
(pF)
50
50
50
50
Typ.
0.3
–0.3
Limit
0.5
–0.5
2.0
0.8
Units
V
V
V
V
Note:
2. Input t
r
=
t
f
=
3ns
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
4
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
AC Electrical Characteristics
T
A
=
+25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C to
+85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
10
7
9.5
6.5
0.5
0.5
7.5
5.0
ns
MHz
ns
ns
Parameter
Propagation Delay,
CP
n
to Q
n
or Q
n
V
CC
(V)
2.7
3.3 ± 0.3
C
L
(pF)
15
50
15
50
15
50
15
50
Min.
Typ.
7.3
9.8
5.7
8.2
8.4
10.9
6.6
9.1
Max.
15
18.5
9.7
13.2
15.6
19.1
10.1
13.6
Max.
18.5
22
11.5
15
18.5
22
12
15.5
Units
ns
t
PLH
, t
PHL
Propagation Delay,
C
Dn
to S
Dn
to Q
n
or Q
n
2.7
3.3 ± 0.3
ns
t
W
t
S
t
H
t
REC
f
MAX
CP
n
or C
Dn
or S
Dn
Pulse
Width
Setup Time, D
n
to CP
n
Hold Time, D
n
to CP
n
Recovery Time,
CP
n
or S
Dn
to CP
n
Maximum Clock
Frequency
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
15
50
15
50
50
8.5
6
8.0
5.5
0.5
0.5
6.5
5.0
55
45
95
60
135
60
145
85
1.5
1.5
ns
50
40
80
50
1.5
1.5
t
OSLH
, t
OSHL
Output to Output Skew
(3)
2.7
3.3
ns
Note:
3. Parameter guaranteed by design t
OSLH
=
|t
PLHm
–t
PLHn
|, t
OSHL
=
|t
PHLm
–t
PHLn
|
Capacitance
T
A
=
+25°C
Symbol
C
IN
C
PD
T
A
=
–40°C to
+85°C
Max.
10
Parameter
Input Capacitance
Power Dissipation Capacitance
(4)
Min.
Typ.
4
25
Min.
Max.
10
Units
pF
pF
Note:
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
C
PD
×
V
CC
×
f
IN
×
I
CC
Average operating current can be obtained by the eqation: I
CC(opr.)
=
--------------------------------------------------------
-
2
(
per
,
F
⁄
F
)
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
www.fairchildsemi.com
5
