74VCX162244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26: Series
Resistor in Outputs
August 1997
Revised June 2005
74VCX162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistor in Outputs
General Description
The VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX162244 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
74VCX162244 is also designed with 26
:
series resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74VCX162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.2V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
:
series resistors in outputs
s
t
PD
3.3 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal
s
Static Drive (I
OH
/I
OL
)
r
12 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX162244G
(Note 2)(Note 3)
74VCX162244MTD
(Note 3)
Package Number
BGA54A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
Ordering Code “G” indicates Trays.
Note 3:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500040
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74VCX162244
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
4
4
OE
2
NC
V
CC
GND
GND
GND
V
CC
NC
OE
3
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Tables
Pin Assignment for FBGA
OE
1
L
L
H
Inputs
OE
2
L
L
H
(Top Thru View)
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
I
12
–I
15
L
H
X
I
8
–I
11
L
H
X
Outputs
O
8
–O
11
L
H
Z
Outputs
O
12
–O
15
L
H
Z
I
4
–I
7
L
H
X
Inputs
I
0
–I
3
L
H
X
Outputs
O
0
–O
3
L
H
Z
Outputs
O
4
–O
7
L
H
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
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2
74VCX162244
Functional Description
The 74VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input. When
OE
n
is LOW, the outputs are in the 2-state mode. When
OE
n
is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Logic Diagram
3
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74VCX162244
Absolute Maximum Ratings
(Note 4)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 5)
DC Input Diode Current (I
IK
) V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
V
O
!
V
CC
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to
4.6V
0.5V to
4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Power Supply
Operating
Data Retention Only
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output in 3-State
Output Current in I
OH
/I
OL
V
CC
V
CC
V
CC
V
CC
V
CC
3.0V to 3.6V
2.3V to 2.7V
1.65V to 2.3V
1.4V to 1.6V
1.2V
0V to V
CC
0.0V to 3.6V
1.2V to 3.6V
1.2V to 3.6V
0.3V to
3.6V
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
r
12 mA
r
8 mA
r
3 mA
r
2 mA
r
100
P
A
40
q
C to
85
q
C
10 ns/V
Note 4:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V
V
CC
d
3.6V)
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
V
IL
LOW Level Input Voltage
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
Min
2.0
1.6
0.65 x V
CC
0.65 x V
CC
0.65 x V
CC
0.8
0.7
0.35 x V
CC
0.35 x V
CC
0.5 x V
CC
V
CC
- 0.2
2.2
2.4
2.2
V
CC
- 0.2
2.0
1.8
1.7
V
CC
- 0.2
1.25
V
CC
- 0.2
1.05
V
CC
- 0.1
V
V
V
Max
Units
100
P
A
6 mA
8 mA
12 mA
100
P
A
4 mA
6 mA
8 mA
100
P
A
3 mA
100
P
A
1 mA
100
P
A
2.7 - 3.6
2.7
3.0
3.0
2.7 - 3.6
2.3
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.2
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4
74VCX162244
DC Electrical Characteristics (2.7V < VCC £ 3.6V)
Symbol
V
OL
Parameter
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
100
P
A
6 mA
8 mA
12 mA
100
P
A
6 mA
8 mA
100
P
A
3 mA
100
P
A
1 mA
100
P
A
Conditions
(Continued)
V
CC
(V)
2.7 - 3.6
2.7
3.0
3.0
2.7 - 3.6
2.3
2.3
0.2
0.4
0.55
0.8
0.2
0.4
0.6
0.2
0.3
0.2
0.35
0.1
V
Min
Max
Units
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.2
1.2 - 3.6
1.2 - 3.6
0
1.2 - 3.6
1.2 - 3.6
2.7 - 3.6
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
I
V
IH
V
IH
or V
IL
V
CC
or GND
V
CC
0.6V
0
d
(V
I
, V
O
)
d
3.6V
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 7)
r
5.0
r
10
10
20
P
A
P
A
P
A
P
A
P
A
r
20
750
'
I
CC
Note 7:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
(Note 8)
Symbol
t
PHL
,
t
PLH
C
L
t
PZL
,
t
PZH
C
L
t
PLZ
,
t
PHZ
C
L
t
OSHL
t
OSLH
Output to Output Skew
(Note 9)
C
L
Note 8:
For C
L
Parameter
Propagation Delay
C
L
Conditions
30 pF, R
L
500
:
V
CC
(V)
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
T
A
40
q
C to
85
q
C
Max
3.3
3.8
7.6
15.2
38
3.8
5.1
9.8
19.6
49
3.6
4.0
7.2
14.4
36
0.5
0.5
0.75
1.5
1.5
Min
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
Units
Figure
Number
Figures
1, 2
ns
Figures
5, 6
Figures
1, 3, 4
ns
Figures
5, 7, 8
Figures
1, 3, 4
ns
Figures
5, 7, 8
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
Output Enable Time
C
L
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
Output Disable Time
C
L
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
C
L
ns
15 pF, R
L
2k
:
1.5
r
0.1
1.2
50
P
F, add approximately 300 ps to the AC maximum specification.
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
5
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