74VHC4066 Quad Analog Switch
April 1994
Revised February 2005
74VHC4066
Quad Analog Switch
General Description
These devices are digitally controlled analog switches uti-
lizing advanced silicon-gate CMOS technology. These
switches have low “on” resistance and low “off” leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the 4066
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. The 4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to V
CC
and
ground.
Features
s
Typical switch enable time: 15 ns
s
Wide analog input voltage range: 0–12V
s
Low “on” resistance: 30 typ. ('4066)
s
Low quiescent current: 80
P
A maximum (74VHC)
s
Matched switch characteristics
s
Individual switch controls
s
Pin and function compatible with the 74HC4066
Ordering Code:
Order Number
74VHC4066M
74VHC4066MX_NL
(Note 1)
74VHC4066MTC
74VHC4066MTCX_NL
(Note 1)
74VHC4066N
Package
Number
M14A
M14A
MTC14
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Description
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC S-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Schematic Diagram
Top View
Truth Table
Input
CTL
L
H
Switch
I/O–O/I
“OFF”
“ON”
© 2005 Fairchild Semiconductor Corporation
DS011677
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74VHC4066
Absolute Maximum Ratings
(Note 2)
(Note 3)
Supply Voltage (V
CC
)
DC Control Input Voltage (V
IN
)
DC Switch I/O Voltage (V
IO
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin
(I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
) (Note 4)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times (t
r
, t
f
)
V
CC
V
CC
V
CC
2.0V
4.5V
9.0V
1000
500
400
ns
ns
ns
2
0
Max
12
V
CC
Units
V
V
0.5 to
15V
1.5 to V
CC
1.5V
V
EE
0.5 to V
CC
0.5V
r
20 mA
r
25 mA
r
50 mA
65
q
C to
150
q
C
600 mW
500 mW
40
85
q
C
Note 2:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 3:
Unless otherwise specified all voltages are referenced to ground.
Note 4:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
(Note 5)
Conditions
V
CC
2.0V
4.5V
9.0V
12.0V
T
A
25
q
C
Typ
1.5
3.15
6.3
8.4
0.5
1.35
2.7
3.6
100
50
30
120
50
35
20
10
5
5
170
85
70
180
80
60
40
15
10
10
T
A
40 to 85
q
C
Guaranteed Limits
1.5
3.15
5.3
8.4
0.5
1.35
2.7
3.6
200
105
85
215
100
75
60
20
15
15
Units
V
V
V
V
V
V
V
V
V
IL
Maximum LOW Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
R
ON
Maximum “ON” Resistance
See (Note 6)
V
CTL
V
IS
V
IH
, I
S
2.0 mA
4.5V
9.0V
12.0V
2.0V
:
:
:
:
:
:
:
:
:
:
P
A
nA
nA
nA
nA
nA
nA
V
CC
to GND
(Figure
1)
V
CTL
V
IS
R
ON
Maximum “ON” Resistance
Matching
I
IN
I
IZ
Maximum Control
Input Current
Maximum Switch “OFF”
Leakage Current
I
IZ
Maximum Switch “ON”
Leakage Current
I
CC
Maximum Quiescent
Supply Current
V
CTL
V
IS
V
IN
V
CC
V
OS
V
IS
V
CTL
V
IS
V
CTL
V
OS
V
IN
I
OUT
V
IH
, I
S
2.0 mA
4.5V
9.0V
12.0V
4.5V
9.0V
12.0V
V
CC
or GND
V
IH
V
CC
to GND
V
CC
or GND
2
6V
V
CC
or GND
GND or V
CC
V
IL
(Figure
2)
V
CC
to GND
V
IH
OPEN (Figure
3)
V
CC
or GND
0
P
A
(Figure
1)
r
0.05
6.0V
9.0V
12.0V
6.0V
9.0V
12.0V
6.0V
9.0V
12.0V
10
15
20
10
15
20
r
0.5
r
600
r
800
r
1000
r
150
r
200
r
300
10
20
40
r
60
r
80
r
100
r
40
r
50
r
60
1.0
2.0
4.0
P
A
P
A
P
A
Note 5:
For a power supply of 5V
r
10% the worst case on resistance (R
ON
) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case V
IH
and V
IL
occur at V
CC
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 6:
At supply voltages (V
CC
– GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
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2
74VHC4066
AC Electrical Characteristics
V
CC
2.0V
6.0V V
EE
0V
12V, C
L
50 pF (unless otherwise specified)
Conditions
V
CC
3.3V
4.5V
9.0V
12.0V
T
A
25
q
C
Typ
25
5
4
3
30
12
6
5
60
25
20
15
40
100
30
10
8
7
58
20
12
10
100
36
32
30
T
A
40 to 85
q
C
Guaranteed Limits
20
13
10
11
73
25
15
13
125
45
40
38
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay Switch In to Out
t
PZL
, t
PZH
Maximum Switch Turn
“ON” Delay
R
L
1 k
:
3.3V
4.5V
9.0V
12.0V
t
PHZ
, t
PLZ
Maximum Switch Turn
“OFF” Delay
R
L
1 k
:
3.3V
4.5V
9.0V
12.0V
Minimum Frequency
Response (Figure
7)
20 log (V
O
/V
I
)
R
L
V
IS
R
L
600
:
2 V
PP
at (V
CC
/2)
600
:
, F
1 MHz
4.5V
9.0V
3 dB
(Note 7)(Note 8)
(Note 8)(Note 9)
R
L
C
L
R
L
600
:
, F
50 pF
600
:
, F
1 MHz
4.5V
9.0V
R
L
F
V
IS
V
IS
10 k
:
, C
L
1 kHz
4 V
PP
8 V
PP
4.5V
9.0V
.013
.008
5
20
V
CTL
GND
0.5
15
10
10
%
%
pF
pF
pF
pF
50 pF,
1 MHz
4.5V
9.0V
4.5V
9.0V
Crosstalk Between
any Two Switches
(Figure
8)
Peak Control to Switch
Feedthrough Noise
(Figure
9)
Switch OFF Signal
Feedthrough
Isolation
(Figure
10)
THD
Total Harmonic
Distortion
(Figure
11)
C
IN
C
IN
C
IN
C
PD
Maximum Control
Input Capacitance
Maximum Switch
Input Capacitance
Maximum Feedthrough
Capacitance
Power Dissipation
Capacitance
Note 7:
Adjust 0 dBm for F
52
50
100
250
dB
dB
mV
mV
V
(CT)
V
IL
(Note 8)(Note 9)
42
44
dB
dB
1 kHz (Null R
L
/R
ON
Attenuation).
Note 8:
V
IS
is centered at V
CC
/2.
Note 9:
Adjust input for 0 dBm.
3
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74VHC4066
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. t
PHL
, t
PLH
Propagation Delay Time Signal Input to Signal Output
FIGURE 5. t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
FIGURE 6. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
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4
74VHC4066
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
5
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