12-Bit A/D Converter
V
REF
AIN1
AIN2
7672
23
V
DD
V
SS
2
+
-
1
24
12-BIT DAC
+
-
22
SUCCESSIVE APPROXIMATION
REGISTER
21
CONTROL
LOGIC
BUSY
12-BIT LATCH
20
19
CS
THREE-STATE
OUTPUT DRIVERS
CLOCK
OSCILLATOR
3
AGND
RD
18
17
CLK OUT
CLK IN
4
D11
11
D4
12
DGND
13
D3
16
D0
Logic Diagram
F
EATURES
:
• 12-bit high speed A/D converter
• R
AD
-P
AK
® radiation-hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effect
- SEL > 120 Mev/mg/cm
2
- SEU
TH
> 5.8 Mev/mg/cm
2
- SEU
Sat
= -1E-4 cm
2
/Device
• Package:
- 24 pin R
AD
-P
AK
® flat package
- 24 pin R
AD
-P
AK
® DIP
• Fast conversion times:
- 7672-05: 5 µs
• Low 110 mW typical power consumption
- Corrects all single-bit errors
- Detects all double and some triple-bit errors
• High-speed BiCMOS technology
- Choice of +5V and +10V input ranges
- Operates with +5V and -12V power supplies
- Fast 125 ns bus-access time
(Si) total dose tolerance, depending upon space mission. The
7672 uses an accurate high-speed DAC and comparator to
achieve conversion time as low as 5 µs while dissipating only
110 mW of power. The 7672 is designed to be used with an
external reference voltage. This allows the user to choose a
reference whose performance suits the application or to drive
multiple 7672s from a single system reference, since the refer-
ence input is buffered and draws very little current. For digital
signal processing applications where absolute accuracy and
temperature coefficients may be unimportant, a low cost refer-
ence can be used. For optimal precision, a high accuracy ref-
erence where an absolute 12-bit accuracy can be obtained
over a wide temperature range may be used. Analog input
range is pin-selectable for 0 to +5V, 0 to +10V, or ±5V, making
the ADC ideal for data acquisition and analog input/output
cards. A high-speed digital interface (125 ns data access time)
with three state data outputs is compatible with most micro-
processors.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
Memory
D
ESCRIPTION
:
Maxwell Technologies
’ 7672 high-speed 12-bit analog-to-
digital converter microcircuit features a greater than 100 krad
Rev 13
08.09.02
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice
1
©2002 Maxwell Technologies
All rights reserved.
12-Bit A/D Converter
T
ABLE
1. 7672 P
INOUT
D
ESCRIPTION
P
IN
1
2
3
4-11
12
13-16
17
18
19
20
21
22
23
24
S
YMBOL
AIN1
V
REF
AGND
D11-D4
DGND
D3-D0
CLKIN
CLKOUT
RD
CS
BUSY
V
SS
V
DD
AIN2
D
ESCRIPTION
Analog Input
Voltage-Reference Input
Analog Ground
Three-State Data Outputs
Digital Ground
Three-State Data Outputs
Clock Input
Clock Output
READ Input
CHIP SELECT
BUSY
Negative Supply, -12V
Positive Supply, +5V
Analog Input
7672
Memory
T
ABLE
2. 7672 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Positive Supply Voltage to DGND
Negative Supply Voltage to DGND
AGND to DGND
AIN1, AIN2 to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
V
REF
to AGND
Power Dissipation to +75°C
Power Dissipation above 75°C (Derate)
Thermal Impedance
Storage Temperature Range
Operating Temperature Range
S
YMBOL
V
DD
V
SS
--
--
V
IN
V
OUT
--
P
D
--
M
IN
-0.3
-17
-0.3
-15
-0.3
-0.3
V
SS
-0.3
--
--
--
-65
-55
M
AX
7.0
+0.3c
V
DD
+0.3
+15
V
DD
+0.3
V
DD
+0.3
V
DD
+0.3
1000
10
3.24
+150
+125
U
NITS
V
V
V
V
V
V
V
mW
mW/°C
°C/W
°C
°C
Θ
JC
T
STG
T
A
08.09.02 REV 13
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
12-Bit A/D Converter
T
ABLE
3. 7672 R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Positive Supply Voltage
Negative Supply Voltage
V
REF
Input Range
Power Dissipation V
DD
= 5V, V
SS
= -12V
S
UBGROUPS
1
1
1
1
S
YMBOL
V
DD
V
SS
V
REF
P
D
M
IN
4.75
-13.2
-5.05
--
M
AX
5.25
-10.8
-4.95
179
7672
U
NITS
V
V
V
mW
T
ABLE
4. 7672 DC E
LECTRICAL
C
HARACTERISTICS
(V
DD
= 5V ±5%, V
SS
= -12V ±10%, V
REF
= -5V, T
A
= -55
TO
125 °C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Output Leakage Current
Input Capacitance
1
Floating State Output Capacitance
2
Power Supply Current
Power Supply Rejection, V
DD
Power Supply Rejection, V
SS
Analog Input Current (AIN1 or AIN2)
V
REF
Input Range
1
V
REF
Input Current
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Unipolar Gain Error
S
YMBOL
V
IL
V
IH
V
OL
V
OH
I
IN
I
LKG
C
IN
C
OUT
I
DD
I
SS
PSRR (V
DD
) V
DD
= 4.75 to 5.25 volts
V
SS
= -12V
PSRR (V
SS
) V
SS
= -10.8 to -13.2 volts
V
DD
= 5V
I
AIN
V
REF
I
REF
RES
INL
DNL
UOE
UGE
T
A
= -55 to +125°C
T
A
= +25 °C
T
A
= -55 to +125°C
12 bits, no missing codes
T
A
= -55 to +125
°
C
T
A
= +25
°
C
T
A
= -55 to +125
°
C
T
A
= +25
°
C
T
A
= -55 to +125
°
C
08.09.02 REV 13
T
EST
C
ONDITION
S
UBGROUPS
1, 2, 3
1, 2, 3
M
IN
--
2.4
--
4.0
--
--
--
--
--
M
AX
0.8
--
0.4
--
±10
±20
±10
10
15
7
-12
±1
±1
±3.5
±1.75
-4.95
±3
--
±1
±1
±0.9
±5
±6
±5
±7
U
NITS
V
V
V
V
µA
µA
pF
pF
mA
LSB
LSB
mA
V
µA
bits
LSB
LSB
LSB
LSB
I
SINK
= 1.6 mA
I
SOURCE
= -200 µA
(CS,RD) V
IN
= V
DD
or GND
(CLKIN) V
IN
= V
DD
or GND
(D0-D11) V
OUT
= V
DD
or GND
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Memory
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
1, 2, 3
1
2, 3
1
2, 3
--
--
--
--
--
--
-5.05
--
12
--
--
--
--
--
--
--
Unipolar Range: 0 to 5 V, 10V
Bipolar Range: ±5V
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
12-Bit A/D Converter
T
ABLE
4. 7672 DC E
LECTRICAL
C
HARACTERISTICS
(V
DD
= 5V ±5%, V
SS
= -12V ±10%, V
REF
= -5V, T
A
= -55
TO
125 °C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Bipolar Zero Error
Bipolar Gain Error
1. Guaranteed by design.
S
YMBOL
BZE
BGE
T
EST
C
ONDITION
T
A
= +25
°
C
T
A
= -55 to +125
°
C
T
A
= +25
°
C
T
A
= -55 to +125
°
C
S
UBGROUPS
1
2, 3
1
2, 3
M
IN
--
--
--
--
M
AX
±5
±6
±5
±7
7672
U
NITS
LSB
LSB
T
ABLE
5. 7672 T
IMING
C
HARACTERISTICS 1,2
(V
DD
= 5V ±5%, V
SS
= -12V ±10%, V
REF
= -5V, T
A
= -55
TO
125 °C
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Conversion Time, Synchronous Clk,
3
Conversion Time, Asynchronous Clk,
CS to RD Setup Time
RD to BUSY Delay
Data Access Time
4
RD Pulse Width
CS to RD Hold Time
Data Setup Time After BUSY4
Bus Relinguish Time
5
Delay Between Read Operations
T
EST
C
ONDITION
12.5 clks, TA = -55 to +125 °C
12-13 clks, TA = -55 to +125 °C
TA = -55 to +125 °C
CL = 50 pF, TA = +25 °C
CL = 50 pF, TA = -55 to +125 °C
CL = 100 pF, TA = +25 °C
CL = 100 pF, TA = -55 to +125 °C
TA = -55 to +125 °C
TA = -55 to +125 °C
CL = 100 pF, TA = +25 °C
CL = 100 pF, TA = -55 to +125 °C
(TA = +25 °C)
(-55 < TA < +125 °C)
(-55 < TA < +125 °C)
S
UBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9
10, 11
9
10, 11
9, 10, 11
9, 10, 11
9
10, 11
9
10, 11
9, 10, 11
S
YMBOL
tCONV
tCONV
t1
t2
t3
t4
t5
t6
--
t7
t8
M
IN
--
4.8
0
--
--
--
--
t3
0
--
--
--
--
200
M
AX
5.0
5.2
--
190
270
125
170
--
--
70
100
75
90
--
U
NITS
us
us
ns
ns
ns
ns
ns
ns
ns
ns
Memory
1. 1LSB = FS/4096; T
A
= 25
°
C; Performance over power supply tolerance is guaranteed by power supply rejection test.
2. All inputs are 0V to +5V swing with t
r
= t
r
= 5ns (10 to 90% of +5V) and timed from a voltage level of +1.6V.
3. Functionally tested.
4. t3 and t6 are measured with the load circuits of Figure 1 and are defined as the time required for an output to cross +0.8 or
+2.4.
5. t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuit of Figure 2.
08.09.02 REV 13
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
12-Bit A/D Converter
F
IGURE
1. L
OAD
C
IRCUITS FOR
A
CCESS
T
IME
7672
F
IGURE
2. L
OAD
C
IRCUIT FOR
B
US
R
ELINQUISH
T
IME
Memory
08.09.02 REV 13
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
