78P2351R
Serial 155M
NRZ to CMI Converter
DATA SHEET
AUGUST 2006
DESCRIPTION
The 78P2351R is Teridian’s second generation Line
Interface Unit (LIU) for 155 Mbit/s electrical SDH
interfaces (STM1e). The device is a single chip
solution that includes an integrated Clock & Data
Recovery in both the transmit and receive paths for
easy, cost efficient NRZ to CMI conversion.
The device interfaces to 75Ω coaxial cable through
wideband transformers and can handle over 12.7dB
of cable loss.
By eliminating the needs for
synchronous clocks, the small 78P2351R (7x7mm
MLF package) is ideal for new STM1e (ES1) Small
Form-factor Pluggable (SFP) transceiver modules.
FEATURES
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ITU-T G.703 compliant, adjustable cable driver
for 155.52 Mbps CMI-coded coax transmission
Integrated adaptive CMI equalizer and CDR in
receive path handles over 12.7dB of cable loss
LVPECL-compatible system interface with
integrated CDR in transmit path for flexible NRZ
to CMI conversion
Configurable via HW control pins or 4-wire serial
port interface
Compliant with ANSI T1.105.03-1994; ITU-T
G.813, G.825, G.958; and Telcordia GR-253-
CORE for jitter performance
Receive Loss of Signal (Rx LOS) detection
Receive Monitor Mode handles up to 20dB of
flat loss (at max 6dB cable loss)
Optional fixed backplane equalizer compensates
for up to 1.5m of trace
Operates from a single 3.3V supply
Available in a small 7x7mm 56-pin QFN
package
Industrial Temperature: -40˚C to +85˚C
APPLICATIONS
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STM1e SFP modules
SDH/ATM Line Cards
Add Drop Multiplexers (ADMs)
PDH/SDH Test Equipment
Digital Microwave Radios
Multi-Service Switches
BLOCK DIAGRAM
78P2351R
Tx Disable
Fixed
Eq.
75ohm Coax
(CMI Encoded)
CDR
TD +
TD -
Adaptive
Eq.
CMI
ENDEC
CDR
RD +
RD -
Rx LOS
LVPECL Data
(NRZ Encoded)
Page: 1 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
78P2351R
Serial 155M
NRZ to CMI Converter
TABLE OF CONTENTS ................................................................................................ 2
FUNCTIONAL DESCRIPTION........................................................................................ 4
REFERENCE CLOCK ............................................................................................................................4
RECEIVER OPERATION .......................................................................................................................4
Receiver Monitor Mode ..................................................................................................................4
Receive Loss of Signal .................................................................................................................4
TRANSMITTER OPERATION ................................................................................................................5
Plesiochronous Mode ....................................................................................................................5
Synchronous Mode ........................................................................................................................5
Clock Synthesizer...........................................................................................................................5
Pulse Amplitude Adjustment.........................................................................................................6
Transmit Backplane Equalizer ......................................................................................................6
POWER-DOWN FUNCTION .................................................................................................................6
LOOPBACK MODES .............................................................................................................................6
POWER-ON RESET ..............................................................................................................................7
SERIAL CONTROL INTERFACE .........................................................................................................7
REGISTER DESCRIPTION............................................................................................. 8
REGISTER ADDRESSING.....................................................................................................................8
REGISTER TABLE.................................................................................................................................8
LEGEND .................................................................................................................................................9
GLOBAL REGISTERS ...........................................................................................................................9
ADDRESS 0-0: MASTER CONTROL REGISTER .........................................................................9
PORT-SPECIFIC REGISTERS ............................................................................................................10
ADDRESS 1-0: MODE CONTROL REGISTER ...........................................................................10
ADDRESS 1-1: SIGNAL CONTROL REGISTER.........................................................................11
ADDRESS 1-2: ADVANCED TX CONTROL REGISTER 1 .........................................................11
ADDRESS 1-3: ADVANCED TX CONTROL REGISTER 0 .........................................................12
ADDRESS 1-4: RESERVED.........................................................................................................12
ADDRESS 1-5: STATUS MONITOR REGISTER.........................................................................12
ADDRESS 1-6, 1-7: RESERVED...................................................................................................13
PIN DESCRIPTION ....................................................................................................... 14
LEGEND ...............................................................................................................................................14
TRANSMITTER PINS ...........................................................................................................................14
RECEIVER PINS ..................................................................................................................................14
REFERENCE AND STATUS PINS ......................................................................................................14
CONTROL PINS ..................................................................................................................................15
SERIAL-PORT PINS ............................................................................................................................16
POWER AND GROUND PINS .............................................................................................................16
Page: 2 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
78P2351R
Serial 155M
NRZ to CMI Converter
TABLE OF CONTENTS
(continued)
ELECTRICAL SPECIFICATIONS ................................................................................. 17
ABSOLUTE MAXIMUM RATINGS..........................................................................................................17
RECOMMENDED OPERATING CONDITIONS ......................................................................................17
DC CHARACTERISTICS.........................................................................................................................17
ANALOG PINS CHARACTERISTICS.....................................................................................................18
DIGITAL I/O CHARACTERISTICS..........................................................................................................18
Pins of type CI, CID ........................................................................................................................18
Pins of type CIT ..............................................................................................................................18
Pins of type CIS ..............................................................................................................................18
Pins of type COZ ............................................................................................................................18
Pins of type PO...............................................................................................................................19
Pins of type PI.................................................................................................................................19
Pins of type OD...............................................................................................................................19
REFERENCE CLOCK CHARACTERISTICS..........................................................................................19
SERIAL-PORT TIMING CHARACTERISTICS........................................................................................20
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE .................................................................21
TRANSMITTER OUTPUT JITTER ..........................................................................................................24
RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled)..................................25
RECEIVER JITTER TOLERANCE ..........................................................................................................26
RECEIVER JITTER TRANSFER FUNCTION .........................................................................................27
LOSS OF SIGNAL CONDITIONS ...........................................................................................................28
APPLICATION INFORMATION .................................................................................... 28
EXTERNAL COMPONENTS ...................................................................................................................28
TRANSFORMER SPECIFICATIONS ......................................................................................................28
THERMAL INFORMATION .....................................................................................................................28
MECHANICAL SPECIFICATIONS ............................................................................... 29
PACKAGE INFORMATION .......................................................................................... 30
ORDERING INFORMATION
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30
Revision History
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Page: 3 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
78P2351R
Serial 155M
NRZ to CMI Converter
FUNCTIONAL DESCRIPTION
The 78P2351R contains all the necessary transmit
and receive circuitry for connection between
155.52Mbit/s NRZ data sources (STS-3/STM-1) and
CMI encoded electrical interfaces (ES1/STM-1e).
The 78P2351R system interface mimics a 3.3V
optical transceiver module and only requires a
reference clock and wideband transformer to
complete the electrical interface. The chip can be
controlled via control pins or serial port register
settings.
In hardware mode (pin control) the SPSL pin must
be low. Additionally, the following unused pins
must be set accordingly:
SDO pin must be tied low
SDI pin must be tied low
SEN pin must be tied high
In software mode (SPSL pin high), control pins set
register defaults upon power-up or reset. The
78P2351R can then be configured via the 4-wire
serial control interface. See Pin Descriptions
section for more information.
REFERENCE CLOCK
The 78P2351R requires a reference clock supplied
to the CKREFP/N pins. For reference frequencies of
19.44MHz or 77.76MHz, the device accepts a single
ended CMOS level input at CKREFP (with CKREFN
pin tied to ground). For reference frequency of
155.52MHz, the device accepts a differential
LVPECL clock input at CKREFP/N. The frequency
of this reference input is selected by either the CKSL
control pin or register bit as follows:
CKSL pin
Low
Float
High
CKSL[1:0] bits
00
10
11
Reference
Frequency
19.44MHz
77.76MHz
155.52MHz
The recovered CMI signal first enters an AGC and
an adaptive equalizer designed to overcome inter-
symbol interference caused by long cable lengths.
The variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
utilizes a line-rate reference frequency derived from
the clock applied to the CKREFP/N pins. After the
clock and data have been recovered, the data is
decoded to binary by the CMI decoder.
The
SODP/N pins output the recovered NRZ data at
LVPECL levels.
Receiver Monitor Mode
The SCK_MON pin or MON register bit puts the
receiver in monitor mode and adds approximately
20dB of
flat gain
to the receive signal before
equalization. Rx Monitor Mode can handle 20dB of
flat loss typical of monitoring points with up to 6dB
(typical 225ft) of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Receive Loss of Signal Detect
The 78P2351R includes a Loss of Signal (LOS)
detector. When the peak value of the received
signal is less than approximately 19dB below
nominal for approximately 110 UI, Receive Loss of
Signal is asserted. The Rx LOS signal is cleared
when the received signal is greater than
approximately 18dB below nominal for 110 UI.
During Rx LOS conditions, the receive clock will
remain on the last phase tap of the Rx DLL
outputting a stable clock while the receive data
outputs are squelched and held at logic ‘0’.
Note:
Rx Loss of Signal detection is disabled
during Local Loopback and Receive Monitor
Modes.
RECEIVER OPERATION
The receiver accepts an ITU-T G.703 compliant CMI
encoded signal at 155.52Mbit/s from the RXP/N
inputs. When properly terminated and transformer-
coupled to the line, the receiver can handle over
12.7dB of cable loss. The receiver’s jitter tolerance
exceeds all relevant standards even with 12.7dB
worth of cable attenuation and inter-symbol
interference (ISI). See Receiver Jitter Tolerance
section for more info.
Page: 4 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
78P2351R
Serial 155M
NRZ to CMI Converter
TRANSMITTER OPERATION
The transmitter section generates an adjustable
ITU-T G.703 compliant analog signal for
transmission through a wideband transformer onto
75Ω coaxial cable. Differential NRZ data is input to
the 78P2351R on the SIDP/N pins at LVPECL levels
and passed to a low jitter clock and data recovery
circuit.
An optional clock decoupling FIFO is
provided to decouple the on chip and off chip clocks.
The NRZ data is encoded using CMI line coding to
ensure an adequate number of transitions.
Each of the transmit timing modes can be configured
in HW mode or SW mode as shown in the table
below.
Tx Mode
Reserved
Synchronous
(FIFO enabled)
Plesiochronous
Loop-timing
Synchronous Mode
When the NRZ transmit data is source synchronous
with the reference clock applied at CKREFP/N as
shown in Figure 2, the 78P2351R can be optionally
used in synchronous mode or re-timing mode. In
this mode, the 78P2351R will recover the clock from
the NRZ data input and re-time the data in an
integrated +/- 4-bit FIFO.
System Reference Clock
CKREFP/N
NRZ
SIDP/N
CMIP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
TDK
78P2351R
SODP/N
RXP/N
CMI
XFMR
Coax
HW Control
CKMODE
Low
Floating
High
n/a
SW Control
SMOD[1:0]
00
10
01
11
Figure 2: Synchronous
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error. If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERR register signal will be asserted. This
signal can be used to trigger an interrupt. This
interrupt event is automatically cleared when a FIFO
Reset (FRST) pulse is applied, and the FIFO is re-
centered.
Notes:
1)
External remote loopbacks (i.e. loopback
within framer) are not possible in
synchronous operation (FIFO enabled)
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2351R is configured for loop-
timing operation.
2)
During IC power-up or transmit power-up,
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow. As such, the FIFO should be
manually reset using FRST anytime the
transmitter is powered-up.
Clock Synthesizer
The transmit clock synthesizer is a low-jitter PLL that
generates a 311.04 MHz clock for the CMI encoder.
A synthesized 155.52 MHz reference clock is also
used in both the receive and transmit sides for clock
and data recovery.
Plesiochronous Mode
Plesiochronous mode represents a common
condition where a synchronous reference clock is
not available. In this mode, the 78P2351R will
recover the transmit clock from the plesiochronous
data and bypass the internal FIFO and re-timing
block. This mode is commonly used for mezzanine
cards, modules, and any application where the
reference clock can’t always be synchronous to the
transmit source clock/data
System
Clock
XO
CKREFP
NRZ
SIDP/N
CMIP/N
CMI
XFMR
Coax
Framer/
Mapper
NRZ
TDK
78P2351R
SODP/N
RXP/N
CMI
XFMR
Coax
Figure 1: Plesiochronous Mode
Page: 5 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
