79C0832
8 Megabit (256K x 32-Bit)
EEPROM MCM
Memory
F
EATURES
:
•
•
•
•
256k x 32-bit EEPROM MCM
R
AD
-P
AK
® radiation-hardened against natural
space radiation
Total dose hardness:
- >100 krad (Si)
- Dependent upon orbit
Excellent Single event effects
- SEL
TH
> 120 MeV/mg/cm
2
- SEU > 90 MeV/mg/cm
2
read mode
- SEU = 18 MeV/mg/cm
2
write mode
High endurance
- 10,000 cycles/byte (Page Programming Mode)
- 10 year data retention
Page Write Mode: 1 to 8 X 128 byte page
High Speed:
- 150 and 200 ns maximum access times
Automatic programming
- 10 ms automatic Page/Byte write
Low power dissipation
- 160 mW/MHz active current
- 880 µ W standby current
D
ESCRIPTION
:
Maxwell Technologies’ 79C0832 multi-chip module (MCM)
memory features a greater than 100 krad (Si) total dose toler-
ance, dependent upon orbit. Using Maxwell Technologies’ pat-
ented radiation-hardened R
AD
-P
AK
® MCM packaging
technology, the 79C0832 is the first radiation-hardened 8
megabit MCM EEPROM for space application. The 79C0832
uses eight 1 Megabit high speed CMOS die to yield an 8
megabit product. The 79C0832 is capable of in-system electri-
cal byte and page programmability. It has a 128 x 8 byte page
programming function to make its erase and write operations
faster. It also features Data Polling and a Ready/Busy signal to
indicate the completion of erase and programming operations.
In the 79C0832, hardware data protection is provided with the
RES pin, in addition to noise protection on the WE signal and
write inhibit on power on and off. Software data protection is
implemented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Maxwell Technologies self-defined Class
K.
•
•
•
•
•
•
02.14.06 REV 15
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2006 Maxwell Technologies
All rights reserved.
8 Megabit (256K x 32-Bit) EEPROM MCM
79C0832
Memory
T
ABLE
1. 79C0832 P
INOUT
D
ESCRIPTION
P
IN
84-77, 29-37
48-55, 66-73, 96,
1-7, 18-25
61
41, 43
45
10, 17, 28, 40, 44,
58, 65, 76, 87, 93
8, 9, 11-16, 26, 27,
38, 42, 46, 56, 57,
59, 60, 62-64, 74,
75, 85, 86, 88-92,
94, 95
39
47
S
YMBOL
ADDR0 to ADDR16
I/O0 to I/O31
OE
CE0-1
WE
5V
GND
D
ESCRIPTION
Address Input
Data Input/Output
Output Enable
Chip Enable 0 through 1
Write Enable
Power Supply
Ground
RDY/BUSY
RES
Ready/Busy
Reset
02.14.06 REV 15
All data sheets are subject to change without notice
2
©2006 Maxwell Technologies
All rights reserved
8 Megabit (256K x 32-Bit) EEPROM MCM
T
ABLE
2. 79C0832 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply Voltage
Input Voltage
Package Weight
S
YMBOL
V
CC
V
IN
RP
RT
XP
Thermal Impedance
Operating Temperature Range
Storage Temperature Range
1. V
IN
min = -3.0V for pulse width <50ns.
F
JC
T
OPR
T
STG
-55
-65
M
IN
-0.6
-0.5
1
45
38
TBD
3
T
YP
79C0832
M
AX
7.0
7.0
U
NIT
V
V
Grams
°
C/W
125
150
°
C
°
C
T
ABLE
3. 79C0832 R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Input Voltage
RES_PIN
Operating Temperature Range
1. V
IL
min = -1.0V for pulse width < 50 ns
S
YMBOL
V
CC
V
IL
V
IH
V
H
T
OPR
M
IN
4.5
-0.3
1
2.2
V
CC
-0.5
-55
M
AX
5.5
0.8
V
CC
+0.3
V
CC
+1
125
U
NIT
V
V
V
V
°
C
Memory
T
ABLE
4. D
ELTA
L
IMITS1
P
ARAMETER
I
CC1A
I
CC1D
I
CC2A
I
LI
- ADDR, CE, OE, WE
V
ARIATION2
+/- 10 %
+/- 10 %
+/- 10 %
+/- 10 %
+/- 10 %
I
LI
- D0-D31
1. Parameters are measured and recorded per MIL-STD-883 for Class K devices
2. Specified value in Table 6
02.14.06 REV 15
All data sheets are subject to change without notice
3
©2006 Maxwell Technologies
All rights reserved
8 Megabit (256K x 32-Bit) EEPROM MCM
T
ABLE
5. 79C0832 C
APACITANCE
(T
A
= 25
°
C, f = 1 MHz)
P
ARAMETER
Input Capacitance : V
IN
= 0V
1
S
YMBOL
C
IN
OE
C
IN
WE
C
IN
CE
0-1
C
IN
A0-A16
C
IN
RES
Output Capacitance: V
OUT
= 0V
1
C
Out
RDY/BSY
C
O ut
D0-D31
1. Guaranteed by design.
--
M
IN
79C0832
M
AX
6
6
6
6
48
6
12
pF
U
NIT
pF
T
ABLE
6. 79C0832 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ±10%, T
A
= -55
TO
+125°C)
P
ARAMETER
Input Leakage Current
1
A0-A16, CE,WE, OE
Input Leakage Current
D0-D31
Standby V
CC
Current
1
T
EST
C
ONDITION
V
IN
= V
CC
V
IN
= 0V
V
IN
=V
CC
I
LI
I
LO
I
CC1A
I
CC1B
I
CC1C
I
CC1D
I
CC2A
1, 2, 3
--
--
1, 2, 3
1, 2, 3
1, 2, 3
--
--
S
YMBOL
I
LI
S
UBGROUPS
1, 2, 3
M
IN
--
M
AX
10
2
1.1
2
4
4
80
4
45
25
60
U
NITS
Memory
µA
mA
µA
µA
µA
mA
mA
mA
mA
Output Leakage Current (V
CC
= 5.5V, V
OUT
= 5.5V/0.4V)
CE = ADDR=WE=OE =V
CC
CE = V
IH;
ADDR=WE=OE =V
CC
CE = ADDR=WE=OE =V
IH
CE =V
IH
, ADDR=WE=OE =0V
Operating
V
CC
Current
1,3
OE = 0V ADDR=WE=V
CC
I
OUT
= 0mA, CE Duty = 100%,
Cycle = 1 us at V
CC
= 5.5V
OE =ADDR=WE=0V
I
OUT
= 0mA, CE Duty = 100%,
Cycle = 1 us at V
CC
= 5.5V
OE = 0V ADDR=WE=V
CC
I
OUT
= 0mA, CE Duty = 100%,
Cycle = 150 ns at V
CC
= 5.5V
OE =ADDR=WE=0V
I
OUT
= 0mA, CE Duty = 100%,
Cycle = 150 ns at V
CC
= 5.5V
Input Voltage
I
CC2B
1, 2, 3
--
85
mA
I
CC2C
1, 2, 3
--
200
mA
I
CC2D
1, 2, 3
225
mA
V
IL
V
IH
RES_PIN
V
H
1, 2, 3
2.2
V
CC
-0.5
0.8
V
02.14.06 REV 15
All data sheets are subject to change without notice
4
©2006 Maxwell Technologies
All rights reserved
8 Megabit (256K x 32-Bit) EEPROM MCM
T
ABLE
6. 79C0832 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ±10%, T
A
= -55
TO
+125°C)
P
ARAMETER
Output Voltage
T
EST
C
ONDITION
S
YMBOL
S
UBGROUPS
M
IN
--
2.4
3.15
V
CC
- 0.3V
79C0832
M
AX
0.4
0.4
--
--
--
U
NITS
V
V
V
V
V
V
OL
Data Lines: V
CC
Min, I
OL
= 2.1mA
1, 2, 3
RDY/BSY_Line: V
CC
Min, I
OL
= 12mA
V
OL
Data Lines: V
CC
Min, I
OH
= -400µ A
V
OH
RDY/BSY_Line: V
CC
Min, I
OH
= -12mA
V
OH
All Outputs: V
CC
Min , I
OH
= -100uA
1. All Inputs are tied to V
CC
with a 5.5KW
resistor, except for RES which is 30KW.
2. For RES I
LI
=800uA max.
3. Only one CE Active (Low)
T
ABLE
7. 79C0832 AC E
LECTRICAL
C
HARACTERISTICS FOR
R
EAD
O
PERATION 1
(V
CC
= 5V ±10%, T
A
= -55
TO
+125°C)
P
ARAMETER
Address Access Time CE = OE = V
IL
, WE = V
IH
-150
-200
Chip Enable Access Time OE = V
IL
, WE = V
IH
-150
-200
Output Enable Access TIme CE = V
IL
, WE = V
IH
-150
-200
Output Hold to Address Change CE = OE =V
IL
, WE = V
IH
-150
-200
Output Disable to High-Z
2
CE = V
IL
, WE = V
IH
-150
-200
CE = OE = V
IL
, WE = V
IH
-150
-200
RES to Output Delay CE = OE = V
IL
, WE = V
IH3
-150
-200
S
YMBOL
t
ACC
S
UBGROUPS
9, 10, 11
--
--
t
CE
9, 10, 11
--
--
t
OE
9, 10, 11
0
0
t
OH
9, 10, 11
0
0
9, 10, 11
t
DF
0
0
t
DFR
0
0
T
RR
9, 10, 11
0
0
450
650
350
450
ns
50
60
ns
ns
--
--
75
125
ns
150
200
ns
150
200
ns
M
IN
M
AX
U
NIT
ns
Memory
1. Test conditions: input pulse levels = 0.4V to 2.4V; input rise and fall times < 20 ns; output load = 1 TTL gate + 100 pF (including
scope and jig); reference levels for measuring timing = 0.8 V/1.8 V.
2. t
DF
and t
DFR
are defined as the time at which the output becomes an open circuit and data is no longer driven.
3. Guaranteed by design.
02.14.06 REV 15
All data sheets are subject to change without notice
5
©2006 Maxwell Technologies
All rights reserved
