33
PRELIMINARY
CY7C1041AV33/
GVT73256A16
256K x 16 Static RAM
Features
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 10, 12 ns
Fast OE access times: 5, 6, and 7 ns
Single +3.3V ±0.3V power supply
Fully static—no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise
immunity
Easy memory expansion with CE and OE options
Automatic CE power-down
High-performance, low power consumption, CMOS
double-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
Functional Description
The CY7C1049AV33\GVT73512A8 is organized as a 262,144
x 16 SRAM using a four-transistor memory cell with a high-per-
formance, silicon gate, low-power CMOS process. Cypress
SRAMs are fabricated using double-layer polysilicon, dou-
ble-layer metal technology.
This device offers center power and ground pins for improved
performance and noise immunity. Static design eliminates the
need for external clocks or timing strobes. For increased sys-
tem flexibility and eliminating bus contention problems, this de-
vice offers Chip Enable (CE), separate Byte Enable controls
(BLE and BHE) and Output Enable (OE) with this organization.
The device offers a low-power standby mode when chip is not
selected. This allows system designers to meet low standby
power requirements.
Functional Block Diagram
VCC
VSS
BLE#
Pin Configuration
SOJ/TSOP II
Top View
A0
DQ1
ADDRESS BUFFER
MEMORY ARRAY
512 ROWS X 256 X 16
COLUMNS
DQ8
DQ9
DQ16
A16
COLUMN DECODER
POWER
DOWN
CE#
BHE#
WE#
OE#
A
0
A
1
A
2
A
3
A
4
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
CC
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
CC
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
Selection Guide
CY7C1049AV33-10/
GVT73512A8-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Com’l/Ind’l
Com’l
L
10
240
10
3.0
CY7C1049AV33-12/
GVT73512A8-12
12
210
10
3.0
Cypress Semiconductor Corporation
•
3901 North First Street
I/O CONTROL
•
San Jose
•
CA 95134
•
408-943-2600
June 15, 2000
PRELIMINARY
Truth Table
Mode
Low Byte Read (DQ
1
–DQ
8
)
High Byte Read (DQ
9
–DQ
16
)
Word Read (DQ
1
–DQ
16
)
Low Byte Write (DQ
1
–DQ
8
)
High Byte Write (DQ
9
–DQ
16
)
Word Write (DQ
1
–DQ
16
)
Output Disable
Standby
CE
L
L
L
L
L
L
L
L
H
WE
H
H
H
L
L
L
X
H
X
OE
L
L
L
X
X
X
X
H
X
BLE
L
H
L
L
H
L
H
X
X
BHE
H
L
L
H
L
L
H
X
X
DQ
1
–D
8
Q
High-Z
Q
D
High-Z
D
High-Z
High-Z
High-Z
CY7C1041AV33/
GVT73256A16
DQ
9
–D
16
High-Z
Q
Q
High-Z
D
D
High-Z
High-Z
High-Z
POWER
Active
Active
Active
Active
Active
Active
Active
Active
Standby
Pin Descriptions
SOJ & TSOP
Pin Numbers
1, 2, 3, 4, 5, 18, 19,
20, 21, 22, 23, 24, 25,
26, 27, 42, 43, 44
17
6
Pin Name
A
0
–A
17
Type
Input
Description
Addresses Inputs: These inputs determine which cell is addressed.
WE
CE
Input
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE
is LOW for a WRITE cycle and HIGH for a READ cycle.
Chip Enable: This active LOW input is used to enable the device. When CE is
LOW, the chip is selected. When CE is HIGH, the chip is disabled and automati-
cally goes into standby power mode.
Byte Enable: These active LOW inputs allow individual bytes to be written or read.
When BLE is LOW, the data is written to or read from the lower byte (DQ
1
–DQ
8
).
When BHE is LOW, the data is written to or read from the higher byte (DQ
9
–DQ
16
).
Output Enable: This active LOW input enables the output drivers.
SRAM Data I/O: Data inputs and data outputs. Lower byte is DQ
1
–DQ
8
and upper
byte is DQ
9
–DQ
16
.
Power Supply: 3.3V ±0.3V%.
Ground.
Power Dissipation ......................................................... 1.0W
Short Circuit Output Current ....................................... 50 mA
39, 40
BLE, BHE
Input
41
7, 8, 9, 10, 13, 14,
15, 16, 29, 30, 31, 32,
35, 36, 37, 38
11, 33
12, 34
OE
DQ
1
–DQ
16
Input
Input/
Output
Supply
Supply
V
CC
V
SS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Voltage on V
CC
Supply Relative to V
SS
......... –0.5V to +4.6V
V
IN
...........................................................–0.5V to V
CC
+0.5V
Storage Temperature (plastic)........................–55°C to +125°
Junction Temperature ..................................................+125°
Note:
1. T
A
is the “Instant On” case temperature.
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[1]
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
2
PRELIMINARY
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
Il
IL
I
IL
O
V
OH
V
OL
V
CC
Parameter
I
CC
I
SB1
I
SB2
Description
Input High (Logic 1) Voltage
[2, 3]
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
[2]
Output Low Voltage
[2]
Supply Voltage
[2]
[2, 3]
CY7C1041AV33/
GVT73256A16
Conditions
Min.
2.2
–0.5
Max.
V
CC
+0.5
0.8
5
5
0.4
Unit
V
V
µA
µA
V
V
V
0V < V
IN
< V
CC
Output(s) disabled, 0V < V
OUT
< V
CC
I
OH
= –4.0 mA
I
OL
= 8.0 mA
–5
–5
2.4
3.0
3.6
Description
Conditions
Power
std.
low
std.
low
std.
low
Typ.
90
25
0.1
-10
240
240
70
70
10
3.0
-12
210
210
60
60
10
3.0
Unit
mA
mA
mA
Power Supply
Device selected; CE < V
IL
; V
CC
= Max.;
Current: Operating
[4, 5]
f = f
MAX
; outputs open
TTL Standby
[5]
CMOS Standby
[5]
CE > V
IH
; V
CC
= Max.; f = f
MAX
CE1 > V
CC
– 0.2; V
CC
= Max.;
all other inputs < V
SS
+ 0.2 or > V
CC
– 0.2;
all inputs static; f = 0
Capacitance
[6]
Parameter
C
I
C
I/O
Description
Input Capacitance
Input/Output Capacitance
(DQ)
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
6
8
Unit
pF
pF
Note:
2. All voltages referenced to V
SS
(GND).
3. Overshoot: V
IH
< +6.0V for t < t
RC
/2.
Undershoot: V
IL
< –2.0V for t < t
RC
/2
4. I
CC
is given with no output current. I
CC
increases with greater output loading and faster cycle times.
5. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
6. This parameter is sampled.
AC Test Loads and Waveforms
3.3V
DQ
Z
0
= 50
Ω
50Ω
Vt = 1.5V
30 pF
ALL INPUT PULSES
3.3V
90%
90%
10%
≤1.5
ns
Fall Time:
1V/ns
0V
10%
317Ω
DQ
351Ω
5 pF
Rise Time:
1V/ns
(a)
(b)
3
PRELIMINARY
Switching Characteristics
[5]
Over the Operating Range
7C1041AV33-10/
GVT73256A16-10
Parameter
READ CYCLE
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
ABE
t
LZBE
t
HZBE
t
PU
t
PD
WRITE CYCLE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP2
t
WP1
t
DS
t
DH
t
LZWE
t
HZWE
t
BW
WRITE Cycle Time
Chip Enable to End of Write
Address Valid to End of Write, with OE HIGH
Address Set-up Time
Address Hold from End of Write
WRITE Pulse Width
WRITE Pulse Width, with OE HIGH
Data Set-up Time
Data Hold Time
Write Disable to Output in Low-Z
Byte Enable to End of Write
[6, 7]
CY7C1041AV33/
GVT73256A16
7C1041AV33-12/
GVT73256A16-12
Min.
12
Max.
Unit
ns
102
12
3
3
ns
ns
ns
ns
6
6
0
6
6
0
6
0
12
12
8
8
0
0
10
8
6
0
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
8
ns
ns
Description
READ Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
[6, 7]
Chip Disable to Output in High-Z
[6, 7, 8]
Output Enable Access Time
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
[6, 8]
Byte Enable Access Time
Byte Enable to Output in Low-Z
[6, 7]
Min.
10
Max.
10
10
3
3
5
5
0
5
5
0
5
0
10
10
8
8
0
0
10
8
5
0
3
5
8
Byte Disable to Output in High-Z
[6, 7, 8]
Chip Enable to Power-up Time
[6]
Chip Disable to Power-down Time
[6]
Write Enable to Output in High-Z
[6, 7, 8]
Data Retention Characteristics
Over the Operating Range (For L version only)
Parameter
V
DR
I
CCDR[9]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE > V
CC
– 0.2V;
all other inputs < V
SS
+ 0.2 or
V
CC
= 3V
>V
CC
– 0.2; all inputs static; f = 0
0
t
RC
Conditions
Min.
2.0
0.2
0.3
1.6
2.4
Typ.
Max.
Unit
V
mA
mA
ns
ns
t
CDR[6]
t
R[6, 10]
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes:
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
.
8. Output loading is specified with C
L
=5 pF as in AC Test Loads. Transition is measured ±500mV from steady state voltage.
9. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads.
10. t
RC
= Read Cycle Time.
4
PRELIMINARY
Low V
CC
Data Retention Waveform
DATA RETENTION MODE
CY7C1041AV33/
GVT73256A16
V
CC
CE#
V
IH
V
IL
t
C D R
3.0V
V
DR
3.0V
t
R C
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDR
t
AA
t
OH
VALID
Q
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2
[7, 11, 13, 14]
t
RC
CE#
t
ABE
t
HZCE
BLE#
BHE#
t
t
LZOE
AOE
t
HZBE
OE#
t
LZBE
t
ACE
t
LZCE
t
HZOE
Q
HIGH Z
DATA VALID
DON'T CARE
UNDEFINED
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected. Chip Enable and Output Enables are held in their active state.
13. Address valid prior to or coincident with latest occurring chip enable.
14. Chip Enable and Write Enable can initiate and terminate a write cycle.
5
