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8102302PA

DUAL OP-AMP, 9000uV OFFSET-MAX, 1MHz BAND WIDTH, CDIP8, CERAMIC, DIP-8

器件类别:模拟混合信号IC    放大器电路   

厂商名称:Rochester Electronics

厂商官网:https://www.rocelec.com/

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Rochester Electronics
零件包装代码
DIP
包装说明
CERAMIC, DIP-8
针数
8
Reach Compliance Code
unknown
放大器类型
OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB)
0.02 µA
标称共模抑制比
86 dB
最大输入失调电压
9000 µV
JESD-30 代码
R-GDIP-T8
长度
9.58 mm
湿度敏感等级
NOT SPECIFIED
负供电电压上限
-18 V
标称负供电电压 (Vsup)
-15 V
功能数量
2
端子数量
8
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, GLASS-SEALED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
筛选级别
MIL-STD-883
座面最大高度
5.08 mm
标称压摆率
3.5 V/us
供电电压上限
18 V
标称供电电压 (Vsup)
15 V
表面贴装
NO
技术
BIPOLAR
温度等级
MILITARY
端子面层
NOT SPECIFIED
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
MIL-STD-883 V
标称均一增益带宽
1000 kHz
宽度
7.62 mm
Base Number Matches
1
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TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
D
D
D
D
D
D
D
D
D
D
Very Low Power Consumption
Typical Supply Current . . . 200
µA
(Per Amplifier)
Wide Common-Mode and Differential
Voltage Ranges
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range
Includes V
CC+
Output Short-Circuit Protection
High Input Impedance . . . JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 3.5 V/
µ
s Typ
TL061, TL061A, TL061B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
OFFSET N1
IN–
IN+
V
CC–
1
2
3
4
8
7
6
5
NC
V
CC+
OUT
OFFSET N2
TL061 . . . U PACKAGE
(TOP VIEW)
description
The JFET-input operational amplifiers of the
TL06_ series are designed as low-power versions
of the TL08_ series amplifiers. They feature high
input impedance, wide bandwidth, high slew rate,
and low input offset and input bias currents. The
TL06_ series feature the same terminal
assignments as the TL07_ and TL08_ series.
Each of these JFET-input operational amplifiers
incorporates well-matched, high-voltage JFET
and bipolar transistors in a monolithic integrated
circuit.
The C-suffix devices are characterized for
operation from 0°C to 70°C. The I-suffix devices
are characterized for operation from –40°C to
85°C, and the M-suffix devices are characterized
for operation over the full military temperature
range of –55°C to 125°C.
NC
OFFSET N1
IN–
IN+
V
CC–
1
2
3
4
5
10
9
8
7
6
NC
NC
V
CC+
OUT
OFFSET N2
TL062, TL062A, TL062B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
V
CC–
1
2
3
4
8
7
6
5
V
CC+
2OUT
2IN–
2IN+
TL062 . . . U PACKAGE
(TOP VIEW)
NC
1OUT
1IN–
1IN+
V
CC–
1
2
3
4
5
10
9
8
7
6
NC
V
CC+
2OUT
2IN–
2IN+
TL064 . . . D, J, N, PW, OR W PACKAGE
TL064A, TL064B . . . D OR N PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
V
CC+
2IN+
2IN–
2OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
4OUT
4IN–
4IN+
V
CC–
3IN+
3IN–
3OUT
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
TL061 . . . FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
NC
NC
TL062 . . . FK PACKAGE
(TOP VIEW)
TL064 . . . FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
VCC+
NC
NC
IN–
NC
IN+
NC
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
V
CC+
NC
OUT
NC
NC
1IN–
NC
1IN+
NC
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
2OUT
NC
2IN–
NC
1IN+
NC
V
CC+
NC
2IN+
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1IN–
1OUT
NC
4OUT
4IN–
4IN+
NC
V
CC–
NC
3IN+
PLASTIC
DIP
(P)
TL061CP
TL061ACP
TL061BCP
TL062CP
TL062ACP
TL062BCP
TSSOP
(PW)
TL061CPW
NC – No internal connection
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOMAX
AT 25°C
15 mV
6 mV
3 mV
0°C
to
70°C
15 mV
6 mV
3 mV
15 mV
6 mV
3 mV
SMALL
OUTLINE
(D008)†
TL061CD
TL061ACD
TL061BCD
TL062CD
TL062ACD
TL062BCD
TL064CD
TL064ACD
TL064BCD
TL064CN
TL064ACN
TL064BCN
SMALL
OUTLINE
(D014)†
PLASTIC
DIP
(N)
CHIP FORM
(Y)
TL061Y
NC
VCC–
NC
OFFSET N2
NC
NC
VCC–
NC
2IN+
NC
TL062CPW
2IN–
2OUT
NC
3OUT
3IN–
TL062Y
TL064CPW
TL064Y
PLASTIC
DIP
(N)
TL064IN
PLASTIC
DIP
(P)
TL061IP
TL062IP
TL061MU
TL062MU
TL064MW
FLAT
PACK
(U)
FLAT
PACK
(W)
PACKAGE
TA
VIOMAX
AT 25°C
SMALL
OUTLINE
(D008)†
TL061ID
TL062ID
SMALL
OUTLINE
(D014)†
TL064ID
TL061MFK
TL062MFK
TL064MFK
TL061MJG
TL062MJG
TL064MJ
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
CERAMIC
DIP
(JG)
–40°C
40 C
to
85°C
–55°C
to
125°C
6 mV
6 mV
6 mV
9 mV
† The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL061CDR).
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
symbol (each amplifier)
IN+
IN–
+
OUT
OFFSET N1
OFFSET N2
Offset Null/Compensation
TL061 Only
schematic (each amplifier)
VCC+
IN+
IN–
50
100
C1
OFFSET N1
OFFSET N2
OUT
VCC–
TL061 Only
C1 = 10 pF on TL061, TL062, and TL064
Component values shown are nominal.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
TL061Y chip information
This chip, when properly assembled, has characteristics similar to the TL061. Thermal compression or
ultrasonic bonding can be used on the doped-aluminum bonding pads. The chips can be mounted with
conductive epoxy or a gold-silicon preform.
Bonding-Pad Assignments
(5)
(6)
(4)
(3)
OFFSET N1
IN+
IN–
(7)
41
OFFSET N2
(5)
(1)
(3)
(2)
VCC+
(7)
+
(4)
VCC–
(6)
OUT
(8)
(1)
(2)
Chip Thickness: 15 Mils Typical
Bonding Pads: 4
×
4 Mils Minimum
TJ(max) = 150°C
Tolerances Are
±10%.
All Dimensions Are in Mils.
Pin (4) is Internally Connected
to Backside of Chip.
53
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
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