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WAN PLL WITH DUAL

REFERENCE INPUTS

FEATURES

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra-

tum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1

interfaces

• Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s inter-

faces

• Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface

and 2048 kbit/s interfaces

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim-

ing for E1 interface

• Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048

MHz

• Accepts reference inputs from two independent sources

• Provides eight types of clock signals: C1.5o,

C3o,

C2o,

C4o,

C6o, C8o,

C16o

and

C32o

• Provides six types of 8 kHz framing pulses:

F0o,

F8o,

F16o,

F32o,

RSP and TSP

•

IDT82V3002A

Holdover frequency accuracy of 0.025 ppm

Phase slope of 5 ns/125 µs

Attenuates wander from 2.1 Hz

Fast Lock mode

Provides Time Interval Error (TIE) correction

MTIE of 600 ns

JTAG boundary scan

Holdover status indication

Freerun status indication

Normal status indication

Lock status indication

Input primary reference quality indication

3.3 V operation with 5 V tolerant I/O

Package available: 56-pin SSOP (Green option available)

DESCRIPTION

The IDT82V3002A is a WAN PLL with dual reference inputs. It

contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS

clocks and framing signals that are phase locked to a 2.048 MHz, 1.544

MHz or 8 kHz input reference.

The IDT82V3002A provides eight types of clock signals (C1.5o,

C3o,

C6o, C2o,

C4o,

C8o,

C16o, C32o)

and six types of framing signals (F0o,

F8o,

F16o, F32o,

RSP, TSP) for the multitrunk T1 and E1 primary rate

transmission links.

The IDT82V3002A is compliant with AT&T TR62411, Telcordia GR-

1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS

300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812

Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets

the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander,

frequency accuracy, capture range, phase change slope, holdover

frequency accuracy and MTIE (Maximum Time Interval Error)

requirements for these specifications.

The IDT82V3002A can be used in synchronization and timing control

for T1 and E1 systems, or used as ST-BUS clock and frame pulse

sources. It can also be used in access switch, access routers, ATM edge

switches, wireless base station controllers, or IADs (Integrated Access

Devices), PBXs and line cards.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

2006

Integrated Device Technology, Inc.

October 15,

2008

DSC-6243/4

IDT82V3002A

WAN PLL WITH DUAL REFERENCE INPUT

FUNCTIONAL BLOCK DIAGRAM

OSCi

OSCo

TCLR

DDD

DDA

OSC

Fref0

Fref1

IN_sel

FLOCK

MON_out

Reference

Input Monitor

Reference

Input Switch

C32o

TIE Control

Block

Virtual

Reference

DPLL

C16o

C8o

C4o

C2o

C3o

C1.5o

C6o

F0o

F8o

F16o

F32o

RSP

TSP

LOCK

RST

Invalid Input

Signal

Detection

Feedback

Signal

TDI

TMS

TRST

JTAG

State Control Circuit

Frequency Select

Circuit

TCK TDO

TIE_en MODE_sel1 MODE_sel0 NORMAL HOLDOVER FREERUN

F_sel1

F_sel0

Figure - 1 Block Diagram

FUNCTIONAL BLOCK DIAGRAM

October 15, 2008

TABLE OF CONTENTS

IDT82V3002A PIN CONFIGURATION........................................................................................................................... 6

PIN DESCRIPTION ........................................................................................................................................................ 7

FUNCTIONAL DESCRIPTION..................................................................................................................................... 10

3.1 State Control Circuit............................................................................................................................................. 10

3.1.1 Normal Mode ............................................................................................................................................11

3.1.2 Fast Lock Mode ........................................................................................................................................ 11

3.1.3 Holdover Mode ......................................................................................................................................... 11

3.1.4 Freerun Mode ........................................................................................................................................... 12

3.2 Frequency Select Circuit...................................................................................................................................... 12

3.3 Reference Input Switch........................................................................................................................................ 12

3.4 Reference Input Monitor ...................................................................................................................................... 12

3.5 Invalid Input Signal Detection .............................................................................................................................. 12

3.6 TIE Control Block................................................................................................................................................. 12

3.7 DPLL Block .......................................................................................................................................................... 15

3.7.1 Phase Detector (PHD) .............................................................................................................................. 15

3.7.2 Limiter ....................................................................................................................................................... 15

3.7.3 Loop Filter................................................................................................................................................. 15

3.7.4 Fraction Block ........................................................................................................................................... 15

3.7.5 Digital Control Oscillator (DCO)................................................................................................................ 16

3.7.6 Lock Indicator ........................................................................................................................................... 16

3.7.7 Output Interface ........................................................................................................................................ 16

3.8 OSC ..................................................................................................................................................................... 16

3.8.1 Clock Oscillator......................................................................................................................................... 16

3.9 JTAG.................................................................................................................................................................... 16

3.10 Reset Circuit ........................................................................................................................................................ 16

3.11 Power Supply Filtering Techniques ..................................................................................................................... 17

MEASURES OF PERFORMANCE .............................................................................................................................. 18

4.1 Intrinsic Jitter........................................................................................................................................................ 18

4.2 Jitter Tolerance .................................................................................................................................................... 18

4.3 Jitter Transfer....................................................................................................................................................... 18

4.4 Frequency Accuracy ............................................................................................................................................18

4.5 Holdover Accuracy............................................................................................................................................... 18

4.6 Capture Range .................................................................................................................................................... 18

4.7 Lock Range.......................................................................................................................................................... 18

4.8 Phase Slope ........................................................................................................................................................ 18

4.9 Time Interval Error (TIE) ...................................................................................................................................... 18

4.10 Maximum Time Interval Error (MTIE) .................................................................................................................. 18

4.11 Phase Continuity.................................................................................................................................................. 19

4.12 Phase Lock Time ................................................................................................................................................. 19

TEST SPECIFICATIONS ............................................................................................................................................. 20

5.1 AC Electrical Characteristics ............................................................................................................................... 21

TIMING CHARACTERISTICS...................................................................................................................................... 25

ORDERING INFORMATION ........................................................................................................................................ 29

October 15, 2008

Table Of Contents

LIST OF FIGURES

Figure - 1

Figure - 2

Figure - 3

Figure - 4

Figure - 5

Figure - 6

Figure - 7

Figure - 8

Figure - 9

Figure - 10

Figure - 11

Figure - 12

Figure - 13

Figure - 14

Figure - 15

Block Diagram .................................................................................................................................................. 2

IDT82V3002A SSOP56 Package Pin Assignment........................................................................................... 6

State Control Block......................................................................................................................................... 10

State Control Diagram.................................................................................................................................... 11

TIE Control Circuit Diagram ........................................................................................................................... 13

Reference Switch with TIE Control Block Enabled......................................................................................... 13

Reference Switch with TIE Control Block Disabled........................................................................................ 14

DPLL Block Diagram ...................................................................................................................................... 15

Clock Oscillator Circuit ................................................................................................................................... 16

Power-Up Reset Circuit.................................................................................................................................. 16

IDT82V3002A Power Decoupling Scheme .................................................................................................... 17

Input to Output Timing (Normal Mode)........................................................................................................... 26

Output Timing 1.............................................................................................................................................. 27

Output Timing 2.............................................................................................................................................. 28

Input Control Setup and Hold Timing ............................................................................................................. 28

List of Figures

October 15, 2008

LIST OF TABLES

Table - 1

Table - 2

Table - 3

Table - 4

Table - 5

Table - 6

Table - 7

Table - 8

Table - 9

Table - 10

Table - 11

Table - 12

Table - 13

Table - 14

Table - 15

Table - 16

Table - 17

Table - 18

Table - 19

Pin Description .................................................................................................................................................. 7

Operating Modes and Status...........................................................................................................................10

Input Reference Frequency Selection ............................................................................................................. 12

Reference Input Switch Control....................................................................................................................... 12

Absolute Maximum Ratings**.......................................................................................................................... 20

Recommended DC Operating Conditions** .................................................................................................... 20

DC Electrical Characteristics** ........................................................................................................................ 20

Performance** ................................................................................................................................................. 21

Intrinsic Jitter Unfiltered................................................................................................................................... 21

C1.5o (1.544 MHz) Intrinsic Jitter Filtered....................................................................................................... 22

C2o (2.048 MHz) Intrinsic Jitter Filtered.......................................................................................................... 22

8 kHz Input to 8 kHz Output Jitter Transfer ..................................................................................................... 22

1.544 MHz Input to 1.544 MHz Output Jitter Transfer..................................................................................... 22

2.048 MHz Input to 2.048 MHz Output Jitter Transfer..................................................................................... 23

8 kHz Input Jitter Tolerance ............................................................................................................................ 23

1.544 MHz Input Jitter Tolerance .................................................................................................................... 23

2.048 MHz Input Jitter Tolerance .................................................................................................................... 24

Timing Parameter Measurement Voltage Levels ............................................................................................ 25

Input / Output Timing....................................................................................................................................... 25

List of Tables

October 15, 2008

型号	82V3002APVG8	82V3002APVG
描述	SSOP-56, Reel	SSOP-56, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology
是否无铅	不含铅	不含铅
是否Rohs认证	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	SSOP	SSOP
包装说明	SSOP-56	SSOP,
针数	56	56
制造商包装代码	PVG56	PVG56
Reach Compliance Code	compliant	compliant
ECCN代码	EAR99	EAR99
Samacsys Confidence	3	3
Samacsys Status	Released	Released
Samacsys PartID	11130143	11130142
Samacsys Pin Count	56	56
Samacsys Part Category	Integrated Circuit	Integrated Circuit
Samacsys Package Category	Small Outline Packages	Small Outline Packages
Samacsys Footprint Name	PVG56-	PVG56
Samacsys Released Date	2020-01-30 04:53:08	2020-01-30 03:46:39
Is Samacsys	N	N
JESD-30 代码	R-PDSO-G56	R-PDSO-G56
JESD-609代码	e3	e3
长度	18.415 mm	18.415 mm
湿度敏感等级	1	1
功能数量	1	1
端子数量	56	56
最高工作温度	85 °C	85 °C
最低工作温度	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260	260
认证状态	Not Qualified	Not Qualified
座面最大高度	2.794 mm	2.794 mm
标称供电电压	3.3 V	3.3 V
表面贴装	YES	YES
电信集成电路类型	TELECOM CIRCUIT	TELECOM CIRCUIT
温度等级	INDUSTRIAL	INDUSTRIAL
端子面层	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
端子形式	GULL WING	GULL WING
端子节距	0.635 mm	0.635 mm
端子位置	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30
宽度	7.5 mm	7.5 mm
Base Number Matches	1	1