Low Skew, 1:6 Crystal-to- LVCMOS/LVTTL
Fanout Buffer
ICS83905
DATA SHEET
General Description
The ICS83905 is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 6 to 12 by utilizing the ability of the
outputs to drive two series terminated lines.
Features
•
•
•
•
•
•
Six LVCMOS / LVTTL outputs
Outputs able to drive 12 series terminated lines
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 80ps (maximum)
RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),
V
DD
= V
DDO
= 2.5V
Offset
Noise Power
100Hz.................-129.7 dBc/Hz
1kHz ...................-144.4 dBc/Hz
10kHz .................-147.3 dBc/Hz
100kHz ...............-157.3 dBc/Hz
ICS
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
mode. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the ICS83905 ideal
for high performance, single ended applications that also require a
limited output voltage.
•
•
•
5V tolerant enable inputs
Synchronous output enables
Operating power supply modes:
Full 3.3V, 2.5V, 1.8V
Mixed 3.3V core/2.5V output operating supply
Mixed 3.3V core/1.8V output operating supply
Mixed 2.5V core/1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
XTAL_OUT
ENABLE2
ENABLE1
XTAL_IN
Pin Assignments
ICS83905
20-Lead VFQFN
4mm x 4mm x 0.925mm
package body
K Package
Top View
20 19 18 17 16
GND 1
GND 2
BCLK0 3
V
DDO
4
BCLK1 5
6
GND
•
•
15 BCLK5
14 V
DDO
13 BCLK4
12 GND
11 GND
7
GND
8
BCLK2
9 10
BCLK3
V
DD
nc
Block Diagram
BCLK0
XTAL_OUT
ENABLE2
GND
BCLK0
V
DDO
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
BCLK1
XTAL_IN
BCLK2
XTAL_OUT
ICS83905
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.38mm package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
BCLK3
BCLK4
ENABLE 1
SYNCHRONIZE
BCLK5
ENABLE 2
SYNCHRONIZE
ICS83905AM REVISION B JULY 20, 2009
1
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Name
XTAL_OUT
XTAL_IN
ENABLE1, ENABLE2
BCLK0, BCLK1, BCLK2,
BCLK3, BCLK4, BCLK5
GND
V
DD
V
DDO
nc
Type
Output
Input
Input
Output
Power
Power
Power
Unused
Description
Crystal oscillator interface. XTAL_OUT is the output.
Crystal oscillator interface. XTAL_IN is the input.
Clock enable. LVCMOS/LVTTL interface levels. See Table 3.
Clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Power supply pin.
Output supply pin.
No connect.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 2.625V
V
DDO
= 2.0V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
7
7
10
Test Conditions
Minimum
Typical
4
19
18
16
Maximum
Units
pF
pF
pF
pF
Ω
Ω
Ω
Function Table
Table 3. Clock Enable Function Table
Control Inputs
ENABLE 1
0
0
1
1
ENABLE2
0
1
0
1
Outputs
BCLK[0:4]
LOW
LOW
Toggling
Toggling
BCLK5
LOW
Toggling
LOW
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
Figure 1. Enable Timing Diagram
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
16 Lead SOIC package
16 Lead TSSOP package
20 Lead VFQFN package
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
78.8°C/W (0 mps)
100.3°C/W (0 mps)
57.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
10
5
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
8
4
Units
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
1.6
1.6
Typical
1.8
1.8
Maximum
2.0
2.0
5
3
Units
V
V
mA
mA
ICS83905AM REVISION B JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4D. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
10
4
Units
V
V
mA
mA
Table 4E. Power Supply DC Characteristics,
3.3V ± 5%, V
DDO
= 1.8V ± 0.2V%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
10
3
Units
V
V
mA
mA
Table 4F. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± 0.2V%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
ENABLE [1:2] = 00
ENABLE [1:2] = 00
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
8
3
Units
V
V
mA
mA
ICS83905AM REVISION B JULY 20, 2009
4
©2009 Integrated Device Technology, Inc.
ICS83905 Data Sheet
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4G. LVCMOS/LVTTL DC Characteristics,
T
A
= 0°C to 70°C
Symbol
Parameter
ENABLE1,
ENABLE2
Test Conditions
V
DD
= 3.3V ± 5%
V
IH
Input High Voltage
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DD
= 3.3V ± 5%
V
IL
Input Low Voltage
ENABLE1,
ENABLE2
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output High Voltage
V
DDO
= 2.5V ± 5%; I
OH
= -1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 2.5V ± 5%; I
OL
= 1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
Minimum
2
1.7
0.65 * V
DD
-0.3
-0.3
-0.3
2.6
2.0
1.8
V
DDO
- 0.3
0.5
0.4
0.45
0.35
V
V
V
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
0.35 * V
DD
Units
V
V
V
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
10
Test Conditions
Minimum
Typical
Fundamental
40
50
7
1
MHz
Maximum
Units
Ω
pF
mW
ICS83905AM REVISION B JULY 20, 2009
5
©2009 Integrated Device Technology, Inc.
