PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-HSTL
FREQUENCY SYNTHESIZER
ICS842256-24
G
ENERAL
D
ESCRIPTION
The ICS842256-24 is a 6 differential HSTL output
Synthesizer designed to generate reference clocks
HiPerClockS™
for SPI-4.2 and XAUI/XGMII 10Gb Ether net
interfaces and is a member of the HiPerClocks™
family of high performance clock solutions from
IDT. Using a 31.25MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings
of frequency select pins: 390.625MHz, 312.5MHz,
195.3125MHz and 156.25MHz.
F
EATURES
• Six differential HSTL output pairs
• Using a 31.25MHz crystal, the two output banks can be
independently set for 390.625MHz, 312.5MHz, 195.3125MHz
or 156.25MHz
• Crystal oscillator interface
• VCO: 1562.5MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
nXTAL_SEL
XTAL_OUT
REF_CLK
PLL_SEL
XTAL_IN
V
DDA
V
DD
IC
S
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies
mentioned above. The ICS842256-24, with low phase noise
VCO tech-nology, can achieve 1ps or lower typical rms phase
jitter, easily meeting SPI-4.2 and 10Gb Ether net jitter
requirements. The ICS842256-24 is packaged in a small
32-pin VFQFN package.
MR
P
IN
A
SSIGNMENT
V
DDO
_
A
QA0
nQA0
QA1
nQA1
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
DIV_SEL_B1
DIV_SEL_B0
DIV_SEL_A1
DIV_SEL_A0
OEB
OEA
V
DD
GND
ICS842256-24
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
K Package
Top View
9 10 11 12 13 14 15 16
V
DDO
_
B
QB1
GND
QB2
nQB1
nQB2
QB3
nQB3
22
21
20
19
18
17
B
LOCK
D
IAGRAM
OEA
Pullup
DIV_SELA[0:1]
Pulldown
PLL_SEL
Pullup
GND
QB0
nQB0
2
0
REF_CLK
Pulldown
XTAL_IN
1
Phase
Detector
OSC
0
VCO
1562.5MHz
÷4
(default)
÷5
÷8
÷16
QA0
nQA0
QA1
nQA1
QB0
1
XTAL_OUT
nXTAL_SEL
Pulldown
÷4
÷8
÷10
(default)
÷16
Feedback Divider
0 = ÷50
(fixed)
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
MR
Pulldown
DIV_SELB[0:1]
Pulldown:Pullup
OEB
Pullup
2
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
1
ICS842256CK-24 REV. A MARCH 29, 2007
ICS842256-24
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Νυ μ β ε ρ
Number
1
2, 3
4, 5
6, 12, 17
7, 8
9, 10
13, 14
15, 16
11
18, 27
19
20
21,
22
23
24
25
26
Ναμ ε
Name
V
DDO_A
QA0, nQA0
QA1, nQA1
GND
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
V
DDO_B
V
DD
OEA
OE B
DIV_SEL_A0,
DIV_SEL_A1
DIV_SEL_B0
DIV_SEL_B1
V
DDA
PLL_SEL
Power
Output
Power
Output
Power
Power
Input
Input
Input
Input
Input
Power
Input
Pullup
Pullup
Τψπ ε
Type
Δ ε σχριπ τιο ½
Description
Output supply pin for Bank A outputs.
Differential clock outputs. HSTL interface levels.
Power supply ground.
Differential clock outputs. HSTL interface levels.
Output supply pins for Bank B outputs.
Core supply pin.
Output enable pin for Bank A outputs. LVCMOS/LVTTL interface levels.
Output enable pin for Bank B outputs. LVCMOS/LVTTL interface levels.
Divide select pins for Bank A outputs. See Table 3A.
Pulldown
LVCMOS/LVTTL interface levels.
Divide select pin for Bank B outputs. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Divide select pin for Bank B outputs. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (QAx, QBx) to go low and the inver ted
28
MR
Input
Pulldown
outputs (nQAx, nQBx) to go high. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
29
REF_CLK
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Selects between the crystal or REF_CLK inputs as the PLL reference
30
nXTAL_SEL
Input
Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
31,
XTAL_OUT,
Crystal oscillator interface. XTAL_OUT is the output.
Input
32
XTAL_IN
XTAL_IN is the input.
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
2
ICS842256CK-24 REV. A MARCH 29, 2007
ICS842256-24
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
DIV_SEL_A1
0
0
1
1
DIV_SEL_A0
0
1
0
1
Feedback
Divider
25
25
25
25
Bank A
Output Divider
4
5
8
16
QA/nQA
Output Frequency
(MHz)
390.625 (default)
312.5
195.3125
97.65625
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
DIV_SEL_B1
0
0
1
1
DIV_SEL_B0
0
1
0
1
Feedback
Divider
25
25
25
25
Bank B
Output Divider
2
4
5
8
QB/nQB
Output Frequency
(MHz)
390.625
195.3125
156.25 (default)
97.65625
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
3
ICS842256CK-24 REV. A MARCH 29, 2007
ICS842256-24
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
37°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_A,
V
DDO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B
I
DD
I
DDA
I
DDO_A,
I
DDO_B
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
V
DD
– 0.10
3.135
Typical
3.3
3.3
3.3
160
10
0
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO_A
= V
DDO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_CLK, MR,
DIV_SELA[0:1],
Input
DIV_SELB0, nXTAL_SEL
High Current
OEA, OEB,
PLL_SEL, DIV_SELB1
REF_CLK, MR,
DIV_SELA[0:1],
Input
DIV_SELB0, nXTAL_SEL
Low Current
OEA, OEB,
PLL_SEL, DIV_SELB1
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IH
I
IL
T
ABLE
4C. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDO_A
= V
DDO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1
0
40
0.6
Typical
Maximum
1.4
0.4
60
1.4
Units
V
V
%
V
V
SWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
4
ICS842256CK-24 REV. A MARCH 29, 2007
ICS842256-24
FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
Fundamental
31.25
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO_A,
V
DDO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
t
sk(o)
t
sk(b)
Parameter
Output
Frequency
QAx/nQAx
QBx/nQBx
Outputs @ Same Frequency
Outputs @ Different Frequencies
390.625MHz (1.875MHz-20MHz)
t
jit(Ø)
RMS Phase Jitter, Random;
NOTE 4
Rise/Fall Time
312.5MHz (1.875MHz-20MHz)
195.3125MHz (1.875MHz-20MHz)
156.25MHz (1.875MHz-20MHz)
t
R
/ t
F
20% to 80%
Test Conditions
Minimum
97.65625
97.65625
TBD
TBD
TBD
0.60
0.58
0.58
0.56
400
Typical
Maximum
390.625
390.625
Units
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
%
Output Skew; NOTE 1, 2
Bank Skew; NOTE 2, 3
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: Please refer to Phase Noise Plots.
IDT
™
/ ICS
™
HSTL FREQUENCY SYNTHESIZER
5
ICS842256CK-24 REV. A MARCH 29, 2007
