FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ
FREQUENCY MARGINING SYNTHESIZER
ICS843101I-100
G
ENERAL
D
ESCRIPTION
The ICS843101I-100 is a low phase-noise
frequency margining synthesizer and is a member
HiPerClockS™
of the HiPerClockS™family of high performance clock
solutions from IDT. In the default mode, the device
nominally generates a 100MHz LVPECL output clock
signal from a 24MHz crystal input. There is also a frequency
margining mode available where the device can be programmed,
using the serial interface, to vary the output frequency up or down
from nominal in 2% steps. The ICS843101I-100 is provided in a
16-pin TSSOP.
F
EATURES
• 100MHz nominal LVPECL output
• Selectable crystal oscillator interface designed for 24MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended input
• Output frequency can be varied ±10% from nominal in 2%
steps
• VCO range: 540MHz - 680MHz
• RMS phase jitter @ 100MHz, using a 24MHz crystal
(1.875MHz - 20MHz): 0.55ps (typical)
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS-6)
packages
IC
S
B
LOCK
D
IAGRAM
OE
CLK
Pullup
Pulldown
P
IN
A
SSIGNMENT
1
V
EE
S_LOAD
S_DATA
S_CLOCK
SEL
OE
V
CCA
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
V
CCO
Q
nQ
V
EE
CLK
XTAL_OUT
XTAL_IN
24MHz
÷P
OSC
0
XTAL_IN
XTAL_OUT
SEL
Phase
Detector
VCO
540 - 680MHz
÷N
Q
nQ
Pulldown
÷M
ICS843101I-100
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
S_CLOCK
S_DATA
S_LOAD
MODE
Pulldown
Pulldown
Pulldown
Pulldown
Serial Control
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
1
ICS843101AGI-100 REV. A APRIL 26, 2007
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
The ICS843101I-100 features a fully integrated PLL and
therefore requires no external components for setting the loop
bandwidth. A 24MHz fundamental crystal is used as the input
to the on chip oscillator. The output of the oscillator is fed into
the pre-divider. In frequency margining mode, the 24MHz crystal
frequency is divided by 2 and a 12MHz reference frequency is
applied to the phase detector. The VCO of the PLL operates
over a range of 540MHz to 680MHz. The output of the M divider
is also applied to the phase detector.
The default mode for the ICS843101I-100 is 100MHz output
frequency using a 24MHz cr ystal. The output frequency
can be changed by placing the device into the margining mode
using the mode pin and using the serial interface to program the
M feedback divider. Frequency margining mode operation occurs
when the MODE input is HIGH. The phase detector and the M
divider force the VCO output frequency to be M times the
reference frequency by adjusting the VCO control voltage. Note
that for some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an output
divider prior to being sent to the LVPECL output buffer. The divider
provides a 50% output duty cycle. The relationship between the
crystal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing back
from frequency margining mode to nominal mode, the device will
return to the default nominal configuration that will provide 100MHz
output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. After shifting
in the 6-bit M divider value, S_LOAD is transitioned from HIGH
to LOW which latches the contents of the shift-register into the
M divider control register. When S_LOAD is LOW, any transitions
of S_CLOCK or S_DATA are ignored.
T
ABLE
1. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
XTAL
(MHz)
24
24
24
24
24
24
24
24
24
24
24
Pre-Divider
(P)
2
2
2
2
2
2
2
2
2
2
2
Reference
Frequency (MHz)
12
12
12
12
12
12
12
12
12
12
12
Feedback
Divider (M)
45
46
47
48
49
50
51
52
53
54
55
M-Data
(Binary)
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
VCO
(MHz)
540
552
564
576
588
600
612
624
636
648
660
Output
Divider (N)
6
6
6
6
6
6
6
6
6
6
6
Output
Frequency
(MHz)
90
92
94
96
98
10 0
102
10 4
10 6
10 8
11 0
% Change
-10.0
-8.0
-6.0
-4.0
-2.0
Nominal Mode
2.0
4. 0
6.0
8.0
10.0
S
ERIAL
L
OADING
S_CLOCK
S_DATA
M5 M4
t
S
M3
M2
M1
M0
t
S
t
H
S_LOAD
Time
F
IGURE
1. S
ERIAL
L
OAD
O
PERATIONS
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
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ICS843101AGI-100 REV. A APRIL 26, 2007
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
T
ABLE
2. P
IN
D
ESCRIPTIONS
Νυ μ β ε ρ
Number
1, 12
2
3
4
5
6
7
8
9, 10
11
13, 14
15
16
Ναμ ε
Name
V
EE
S_LOAD
S_DATA
S_CLOCK
SEL
OE
V
CCA
V
CC
XTAL_IN,
XTAL_OUT
CL K
nQ, Q
V
CCO
MODE
Τψπ ε
Type
Power
Input
Input
Input
Input
Input
Power
Power
Input
Input
Oupu t
Power
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Δ ε σχριπ τιο ½
Description
Negative supply pins.
Controls the operation of the Serial input. LVCMOS/LVTTL interface levels.
See Table 4D.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels. See Table 4D.
Clock in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. See Table 4D.
Select pin. When HIGH, selects CLK input. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels. See Table 4B.
Output enable pin. Controls enabling and disabling of Q/nQ outputs.
LVCMOS/LVTTL interface levels. See Table 4A.
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Pulldown LVCMOS/LVTTL clock input.
Differential output pair. LVPECL interface levels.
Output supply pin.
Pulldown MODE pin. LVCMOS/LVTTL interface levels. See Table 4C.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
3
ICS843101AGI-100 REV. A APRIL 26, 2007
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
T
ABLE
4A. OE C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
OE
0
1
Outputs
Q , nQ
Hi Z
Enabled
T
ABLE
4B. SEL C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
SEL
0
1
Selected Source
XTAL_IN, XTAL_OUT
CLK
T
ABLE
4C. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
Mode
0
1
Condition
Q, nQ
Default Mode
Frequency Margining Mode
T
ABLE
4D. S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
S_LOAD
L
H
S_CLOCK
X
↑
S_DATA
X
Data
Serial inputs are ignored.
Serial input mode.
Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are latched.
Conditions
L
X
↓
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
4
ICS843101AGI-100 REV. A APRIL 26, 2007
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
89°C/W (0 mps)
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, , V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.10
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
115
100
10
8
Units
V
V
V
mA
mA
mA
mA
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%,V
CCO
= 2.5V±5%, , V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.10
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
115
100
10
8
Units
V
V
V
mA
mA
mA
mA
T
ABLE
5C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.5V±5%, , V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
CC
– 0.10
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
CC
2.625
110
100
10
8
Units
V
V
V
mA
mA
mA
mA
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
5
ICS843101AGI-100 REV. A APRIL 26, 2007
