700MHz/350MHz, Crystal-to-3.3V LVPECL
Frequency Synthesizer
General Description
The ICS8432-11 is a general purpose, dual output Crystal-to-3.3V
Differential LVPECL High Frequency Synthesizer. The ICS8432-11
has a selectable TEST_CLK or crystal inputs. The TEST_CLK input
accepts LVCMOS or LVTTL levels and translates them to 3.3V
LVPECL levels. The VCO operates at a frequency range of 200MHz
to 700MHz. The VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. Output frequencies
up to 700MHz for FOUT and 350MHz for FOUT/2 can be
programmed using the serial or parallel interfaces to the
configuration logic.
ICS8432-11
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
TEST_CLK can accept the following input levels: LVCMOS or
LVTTL
Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
VCO range: 200MHz to 700MHz
Parallel interface for programming counter and VCO frequency
multiplier and dividers
RMS period jitter: 25ps (maximum)
Cycle-to-cycle jitter: 65ps (maximum)
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
VCO_SEL
Pullup
XTAL_SEL
Pullup
TEST_CLK
Pulldown
XTAL_IN
Pin Assignment
XTAL_OUT
VCO_SEL
nP_LOAD
M4
M3
M1
0
32 31 30 29 28 27 26 25
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9
TEST
M0
M2
OSC
XTAL_OUT
1
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
FOUT
nFOUT/2
FOUT/2
nFOUT
V
CC
V
CCO
V
EE
XTAL_IN
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
N0
N1
Phase Detector
MR
Pulldown
VCO
÷M
0
÷N
1
÷2
nc
FOUT
nFOUT
FOUT/2
nFOUT/2
V
EE
S_LOAD
Pulldown
S_DATA
Pulldown
S_CLOCK
Pulldown
nP_LOAD
Pulldown
Configuration Interface Logic
TEST
M0:M8
M5 Pullup; M[0:4, 6:8] Pulldown
N0:N1
Pulldown
ICS8432-11
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432CY-11 REVISION A DECEMBER 1, 2010
1
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
25MHz clock input provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 200MHz to
700MHz. The output of the M divider is also applied to the phase
detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note, that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-11 support two input
modes to program the PLL M divider and N output divider. The two
input operational modes are parallel and serial.
Figure1
shows the
timing diagram for each mode. In parallel mode, the nP_LOAD input
is initially LOW. The data on inputs M0 through M8 and N0 and N1 is
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hardwired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the input frequency
and the M divider is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 8
≤
M
≤
28. The frequency out is defined as follows:
fOUT = fVCO = fXTAL x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_DATA, Shift Register Input
Output of M Divider
CMOS FOUT/2
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
*NULL
N1
H
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
ICS8432CY-11 REVISION A DECEMBER 1, 2010
2
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
V
EE
TEST
V
CC
FOUT/2, nFOUT/2
V
CCO
FOUT, nFOUT
Input
Input
Type
Pullup
Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Half frequency differential output for the synthesizer.
LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs FOUTx to go low and the inverted outputs
nFOUTx to go high. When Logic LOW, the internal dividers and the
outputs are enabled. Assertion of MR does not affect loaded M, N, and T
values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on
the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Pulldown
Selects between crystal or test clock inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Pulldown
Parallel load input. Determines when data present at M8:M0 is loaded
into M divider, and when data present at N1:N0 sets the N output divider
value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode. When LOW,
synthesizer is in bypass mode, when HIGH synthesizer is in PLL mode.
LVCMOS/LVTTL interface levels.
Description
Input
Unused
Power
Output
Power
Output
Power
Output
Pulldown
17
MR
Input
Pulldown
18
19
20
21
22
23
24,
25
26
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
nP_LOAD
Input
Input
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Input
27
VCO_SEL
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
3
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces true outputs LOW.
Data on M and N inputs passed directly to the M divider.
TEST output forced LOW.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L =
H=
X=
↑
=
↓
=
DC =
LOW
HIGH
Don’t care = static DC level
Rising edge transition
Falling edge transition
LOW or HIGH
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
200
225
250
275
•
•
650
675
700
256
M Divide
8
9
10
11
•
•
26
27
28
M8
0
0
0
0
•
•
0
0
0
128
M7
0
0
0
0
•
•
0
0
0
64
M6
0
0
0
0
•
•
0
0
0
32
M5
0
0
0
0
•
•
0
0
0
16
M4
0
0
0
0
•
•
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
4
M2
0
0
0
0
•
•
0
0
1
2
M1
0
0
1
1
•
•
1
1
0
1
M0
0
1
0
1
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal frequency of 25MHz.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
4
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 3C. Programmable Output Divider Function Table
Output Frequency (MHz)
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Minimum
200
100
50
25
FOUT
Maximum
700
350
175
87.5
Minimum
125
62.5
31.25
15.625
FOUT/2
Maximum
350
175
87.5
43.75
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
65.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.17
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
177
17
Units
V
V
V
mA
mA
ICS8432CY-11 REVISION A DECEMBER 1, 2010
5
©2010 Integrated Device Technology, Inc.
