Low Skew, 1-to-4
Differential-to-LVHSTL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 8523I-03 is a low skew, high performance 1-to-4 Dif-
ferential-to-LVHSTL fanout buffer. The 8523I-03 has two
selectable clock inputs.The input pairs can accept most
standard differential input levels. The clock enable is
internally synchronized toeliminate runt pulses on the
outputs during asynchronousassertion/deassertion of the clock
enable pin.
Guaranteed output and par t-to-par t skew character-
istics make the 8523I-03 ideal for those applications
demanding well defined performance and repeatability.
8523I-03
DATA SHEET
F
EATURES
•
4 differential LVHSTL compatible outputs
•
Selectable differential CLK0, nCLK0 and CLK1, nCLK1
clock inputs
•
Clock input pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 650MHz
•
Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 400ps (maximum)
•
Propagation delay: 1.2ns (typical)
•
V
OH
= 1V (maximum)
•
3.3V core, 1.8V output operating supply
•
Lead-Free package available
•
-40°C to 85°C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
GND
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
8523I-03
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523I-03 REVISION A 11/9/15
1
©2015 Integrated Device Technology, Inc.
8523I-03 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
GND
CLK_EN
Power
Input
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup
Pullup
Inverting differential clock input.
Inverting differential clock input.
No connect.
Core supply pin.
Differential output pair. LVHSTL interface levels.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Pulldown Non-inverting differential clock input.
3
4
5
6
7
8, 9
10
11, 12
13, 18
14, 15
16, 17
19, 20
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
V
DD
nQ3, Q3
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
2
REVISION A 11/9/15
8523I-03 DATA SHEET
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 , nCLK0 and CLK1, nCLK1 inputs as described
in Table 3B.
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK0 or nCLK1
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ3
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
REVISION A 11/9/15
3
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
8523I-03 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
55
Units
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.15
1.3
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
0.5
V
DD
- 0.85
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
4
REVISION A 11/9/15
8523I-03 DATA SHEET
T
ABLE
4D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
0.7
0
0.4
Typical
Maximum
1.0
0.4
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ > 200MHz
ƒ
≤
200MHz
150
45
48
50
ƒ
≤
650MHz
0.9
1.2
Test Conditions
Minimum
Typical
Maximum
650
1.5
50
400
500
55
52
Units
MHz
ns
ps
ps
ps
%
%
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
REVISION A 11/9/15
5
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
