Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
Sixteen differential 3.3V LVPECL outputs
•
CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 500MHz
•
Translates any single-ended input signal to
3.3V LVPECL levels with a resistor bias on nCLK input
•
Output skew: 75ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Additive phase jitter, RMS: 0.03ps (typical)
•
3.3V output operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS8530-01 is a low skew, 1-to-16 Differen-
tial-to-3.3V LVPECL Fanout Buffer and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS8530-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK
nCLK
P
IN
A
SSIGNMENT
nCLK
V
CCO
Q15
nQ15
Q14
nQ14
V
EE
Q13
nQ13
Q12
nQ12
V
CCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
Vcco
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8530DY-01
www.icst.com/products/hiperclocks.html
1
V
CCO
nQ4
Q4
nQ5
Q5
V
EE
nQ6
Q6
nQ7
Q7
V
CCO
V
CC
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Type
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Core supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 11, 14, 24,
25, 35, 38, 48
2, 3
4, 5
6, 19, 30, 43
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
36
37
39, 40
41, 42
44, 45
46, 47
NOTE:
Pullup
and
Name
V
CCO
Q11, nQ11
Q10, nQ10
V
EE
Q9, nQ9
Q8, nQ8
V
CC
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
CL K
Input
Pulldown Non-inver ting differential clock input.
nCLK
Input
Pullup
Inver ting differential clock input.
Differential output pair. LVPECL interface levels.
Q15, nQ15
Output
Q14, nQ14
Output
Differential output pair. LVPECL interface levels.
Output
Differential output pair. LVPECL interface levels.
Q13, nQ13
Differential output pair. LVPECL interface levels.
Q12, nQ12
Output
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q15
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ15
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8530DY-01
www.icst.com/products/hiperclocks.html
2
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Input/core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
140
Units
V
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
-2V.
8530DY-01
www.icst.com/products/hiperclocks.html
3
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
IJ 500MHz
Minimum
1
88
106.25MHz, Integration
Range: 12KHz to 20MHz
20% to 80% @ 50MHz
20% to 80% @ 50MHz
0.03
300
300
700
700
53
Typical
Maximum
500
2
75
250
Units
MHz
ns
ps
ps
ps
ps
ps
%
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
47
50
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8530DY-01
www.icst.com/products/hiperclocks.html
4
REV. E MAY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS8530-01
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 106.25MHz (12KHz to 20MHz)
= 0.03ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
8530DY-01
www.icst.com/products/hiperclocks.html
5
REV. E MAY 19, 2006
stm32/stm8
