Low Skew, 1-to-6,
Differential-to-LVDS Fanout Buffer
Datasheet
854S006
Description
The 854S006 is a low skew, high performance 1-to-6,
Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept
most standard differential input levels. The 854S006 is
characterized to operate from either a 2.5V or a 3.3V power
supply.
Guaranteed output and part-to-part skew characteristics
make the
854S006
ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
▪
Six differential LVDS outputs
▪
One differential clock input pair
▪
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
▪
Maximum output frequency: 1.7GHz
▪
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
▪
Output Skew: 55ps (maximum)
▪
Propagation delay: 850ps (maximum)
▪
Additive phase jitter, RMS: 0.067ps (typical)
▪
Full 3.3V or 2.5V supply
▪
-40°C to 85°C ambient operating temperature
▪
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
CLK
nCLK
Pull-up
Pull-down
Pin Assignment
nCLK
CLK
V
DD
V
DDO
Q0
nQ0
GND
Q1
nQ1
V
DDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
GND
V
DD
V
DDO
nQ5
Q5
GND
nQ4
Q4
V
DDO
nQ3
Q3
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
©2017 Integrated Device Technology, Inc.
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April 11, 2017
854S006 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3, 22
4, 10, 15, 21
5, 6
7, 18, 23, 24
8, 9
11, 12
13, 14
16, 17
19, 20
Name
nCLK
CLK
V
DD
V
DDO
Q0, nQ0
GND
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Type
[a]
Input (PD)
Input (PU)
Power
Power
Output
Power
Output
Output
Output
Output
Output
Inverting differential clock input.
Description
Non-inverting differential clock input.
Positive supply pins.
Output supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
[a] Pull-up (PU) and pull-down (PD) refer to internal input resistors, and are indicated in parentheses.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3. Clock Input Function Table
Inputs
CLK
0
1
0
1
Biased
[a]
Biased
[a]
nCLK
1
0
Biased
[a]
Biased
[a]
0
1
Q[0:5]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ[0:5]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input-to-Output Mode
Differential to Differential
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
[a] Refer to the Application Information section,
Wiring the Differential Input to Accept Single-ended Levels.
©2017 Integrated Device Technology, Inc.
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April 11, 2017
854S006 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 854S006 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 4. Absolute Maximum Ratings
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+0.5V
10mA
15mA
70C/W (0mps)
-65C to 150C
Rating
DC Electrical Characteristics
C
Table 5. Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
55
105
Units
V
V
mA
mA
Table 6. Power Supply DC Characteristics, V
DD
= V
DDO
= 2.5V ±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
55
102
Units
V
V
mA
mA
©2017 Integrated Device Technology, Inc.
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854S006 Datasheet
Table 7. Differential DC Characteristics, V
DD
= V
DDO
= 3.3V ±5% or 2.5V ±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
Minimum
Typical
Maximum
10
150
Units
µA
µA
µA
µA
-150
-10
0.15
GND +0.5
1.3
V
DD
– 0.85
Peak-to-Peak Input Voltage
[a]
Common Mode Input Voltage
[a][b]
V
V
[a] V
IL
should not be less than -0.3V.
[b] Common mode voltage is defined as V
IH
.
Table 8. LVDS DC Characteristics, V
DD
= V
DDO
= 3.3V ±5%, T
A
= -40°C to 85°C
[a]
Symbol
V
OD
V
OD
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
326
1.28
Typical
Maximum
526
50
1.44
50
Units
mV
mV
V
mV
V
OS
[a] For output information, refer to the
Parameter Measurement Information.
Table 9. LVDS DC Characteristics, V
DD
= V
DDO
= 2.5V ±5%, T
A
= -40°C to 85°C
[a]
Symbol
V
OD
V
OD
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
305
1.1
Typical
Maximum
505
50
1.45
50
Units
mV
mV
V
mV
V
OS
[a] For output information, refer to the
Parameter Measurement Information.
©2017 Integrated Device Technology, Inc.
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April 11, 2017
854S006 Datasheet
AC Electrical Characteristics
Table 10. AC Characteristics, V
DD
= V
DDO
= 3.3V ±5%, T
A
= -40°C to 85°C
[a]
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay
[b]
Output Skew
[c][d]
Part-to-Part Skew
[d][e]
Buffer Additive Phase Jitter, RMS;
see
Additive Phase Jitter
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
Minimum
0
300
Typical
Maximum
1.7
850
55
150
Units
GHz
ps
ps
ps
ps
622.08MHz,
Integration Range: 12kHz
―
5MHz
20% to 80%
≤1.2GHz
50
47
0.067
250
53
ps
%
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[b] Measured from the differential input crossing point to the differential output crossing point.
[c] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing point.
[d] This parameter is defined in accordance with JEDEC Standard 65.
[e] Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 11. AC Characteristics, V
DD
= V
DDO
= 2.5V ±5%, T
A
= -40°C to 85°C
[a]
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay
[b]
Output Skew
[c][d]
Part-to-Part Skew
[d][e]
Buffer Additive Phase Jitter, RMS;
see
Additive Phase Jitter
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
Minimum
0
300
Typical
Maximum
1.7
800
55
150
Units
GHz
ps
ps
ps
ps
622.08MHz,
Integration Range: 12kHz
―
5MHz
20% to 80%
≤1.2GHz
50
47
0.067
250
53
ps
%
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[b] Measured from the differential input crossing point to the differential output crossing point.
[c] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing point.
[d] This parameter is defined in accordance with JEDEC Standard 65.
[e] Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
©2017 Integrated Device Technology, Inc.
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April 11, 2017
