FemtoClock® NG Differential-to-3.3V,
2.5V LVPECL Synthesizer
8N3PG10MBKI-161
Data Sheet
General Description
The 8N3PG10MBKI-161 is a very versatile programmable LVPECL
synthesizer that can be used for OTN/SONET to Ethernet or 10GB
Ethernet to OTN/SONET rate conversions. The conversion rate is
pin-selectable and one of the four rates is supported at a time. In the
default configuration, an input clock of 156.25MHz is converted to
161.1328125MHz output (dithering off).
The device uses IDT’s fourth generation FemtoClock
®
NG
technology to deliver low phase noise clocks combined with low
power consumption. The RMS phase jitter at 161.1328125MHz
output frequency is 0.567ps (12kHz - 20MHz integration range).
Features
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock
®
Next Generation (NG)
technology
Footprint compatible with 5mm x 7mm differential oscillators
One differential LVPECL output pair
CLK, nCLK input pair can accept the following levels: HCSL,
LVDS, LVPECL, LVHSTL
Output frequency: 161.1328125MHz
RMS phase jitter, 12kHz – 20MHz = 0.567ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Frequency Select Table
FSEL[1:0]
00
01
10
11
Input (MHz)
156.25
156.25
156.25
156.25
Output Frequency (MHz)
161.1328125
161.1328125
161.1328125
161.1328125 (default)
Block Diagram
OE
CLK
nCLK
Pullup
Pulldown
PU/PD
Pin Assignment
FSEL1
PFD
&
FemtoClock
®
NG
VCO
÷N
Q
OE
1
10
9
FSEL0
8
V
CC
7
nQ
5 6
CLK
Q
nc
2
÷M
FSEL0
FSEL1
Pullup
Pullup
V
EE
3 4
nCLK
Control
Logic
8N3PG10MBKI-161
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A January 28, 2016
8N3PG10MBKI-161 Data Sheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6, 7
8
9
10
Name
OE
Reserved
V
EE
nCLK
CLK
Q, nQ
V
CC
FSEL0
FSEL1
Reserve
Power
Input
Input
Output
Power
Input
Input
Pullup
Pullup
Pullup/
Pulldown
Pulldown
Type
Pullup
Description
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
Reserved pin.
Negative supply pin.
Inverting differential clock input. V
CC
/2 default when left floating
Non-inverting differential clock input.
Differential output pair. LVPECL interface levels.
Power supply pin.
Feedback control input. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See
Frequency Select Table
on page 1.
Feedback control input. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See
Frequency Select Table
on page 1.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. P, M, N Divider Function Table
FSEL[1:0]
00
01
10
1 1 (default)
P
÷2
÷2
÷2
÷2
M
÷28.87500
÷28.87500
÷28.87500
÷28.87500
N
÷14
÷14
÷14
÷14
Input Frequency
(MHz)
156.25
156.25
156.25
156.25
Output Frequency
(MHz)
161.1328125
161.1328125
161.1328125
161.1328125
©2016 Integrated Device Technology, Inc
2
Revision A January 28, 2016
8N3PG10MBKI-161 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
CC
+ 0.5V
50mA
100mA
39.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
151
Maximum
3.465
189
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
146
Maximum
2.625
182
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
OE,
FSEL[1:0]
OE,
FSEL[1:0]
V
CC
= 3.465V
V
CC
= 2.625V
Input High Current
Input Low Current
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
©2016 Integrated Device Technology, Inc
3
Revision A January 28, 2016
8N3PG10MBKI-161 Data Sheet
Table 4D. Differential DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High Current
CLK, nCLK
CLK
I
IL
Input
Low Current
nCLK
V
PP
V
CMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input
Voltage; NOTE 1, 2
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
-5
-150
0.15
V
EE
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as the crossing point.
Table 4E. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.6
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
©2016 Integrated Device Technology, Inc
4
Revision A January 28, 2016
8N3PG10MBKI-161 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
f
OUT
= 161.1328125MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
150
49
Test Conditions
Minimum
Typical
161.1328125
18
0.567
450
51
30
Maximum
Units
MHz
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Refer to the Phase Noise plots.
NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks.
Table 5B. AC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter;
NOTE 1
RMS Phase Jitter (Random);
NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
f
OUT
= 161.1328125MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
100
49
Test Conditions
Minimum
Typical
161.1328125
18
0.567
500
51
30
Maximum
Units
MHz
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Refer to the Phase Noise plots.
NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks.
©2016 Integrated Device Technology, Inc
5
Revision A January 28, 2016
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