Quad-Frequency Programmable XO IDT8N4Q001 REV G
DATA SHEET
General Description
The IDT8N4Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4Q001 can be programmed via the I
2
C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷
N
(N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to four
independent PLL divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency and
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVDS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
f
XTAL
÷MINT,
MFRAC
2
25
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
DNU 1
OE 2
GND 3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
DD
7 nQ
6 Q
7
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
IDT8N4Q001
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Table 1. Pin Descriptions
Number
1
2
3
5, 4
6, 7
8
9
10
Name
DNU
OE
GND
FSEL1, FSEL0
Q, nQ
V
DD
SDATA
SCLK
Input
Power
Input
Output
Power
Input
Input
Pullup
Pullup
Pulldown
Pullup
Type
Description
Do not use.
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Default frequency select pins. See the Default Frequency Order Codes section.
LVCMOS/LVTTL interface levels.
Differential clock output. LVDS interface levels.
Power supply pin.
I
2
C Data Input. LVCMOS/LVTTL interface levels.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
5.5
50
50
Maximum
Units
pF
k
k
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
Output Frequency Ranges
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
2
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Block Diagram with Programming Registers
PFD
&
LPF
Output Divider N
FemtoClock® NG
VCO
1950-2600MHz
÷
N
Q
nQ
OSC
f
XTAL
MHz
2
÷P
Feedback Divider M (25 Bit)
MINT
(7 bits)
7
MFRAC
(18 bits)
7
18
27
34
Programming Registers
P0
MINT0
7 bits
7 bits
MINT1
7 bits
7 bits
MINT2
7 bits
7 bits
MINT3
7 bits
7 bits
MFRAC0
18 bits
18 bits
MFRAC1
18 bits
18 bits
MFRAC2
18 bits
18 bits
MFRAC3
18 bits
18 bits
N0
7 bits
7 bits
N1
7 bits
7 bits
N2
7 bits
7 bits
N3
7 bits
7 bits
34
34
34
34
I C Control
30
2
I
2
C:
Def:
2 bits
2 bits
P1
00
I
2
C:
30
Def:
2 bits
2 bits
P2
01
SCLK
SDATA
Pullup
Pullup
I
2
C:
30
Def:
2 bits
2 bits
P3
34
10
I
2
C:
30
Def:
2 bits
2 bits
11
FSEL[1:0]
OE
Pulldown, Pulldown
Pullup
Def: Power-up default register setting for I
2
C registers
Pn, MINTn, MFRACn and Nn
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
3
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Principles of Operation
The block diagram consists of the internal 3
rd
overtone crystal and
oscillator which provide the reference clock f
XTAL
of either 114.285
MHz or 100MHz. The PLL includes the FemtoClock NG VCO along
with the Pre-divider (P), the feedback divider (M) and the post divider
(N). The
P, M,
and
N
dividers determine the output frequency based
on the f
XTAL
reference and must be configured correctly for proper
operation. The feedback divider is fractional supporting a huge
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase
noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set
P, M,
and
N
configuration settings. These
default pre-sets are stored in the I
2
C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read
back using the SCLK and SDATA pins.
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I
2
C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
If the user does choose to write a different
P, M,
and
N
configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I
2
C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency f
OUT
is
calculated by:
As identified previously, the configurations of
P, M (MINT & MFRAC)
and
N
divider settings are stored the I
2
C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
FSEL1
0 (def.)
0
1
1
FSEL0
0 (def.)
1
0
1
Selects
Frequency 0
Frequency 1
Frequency 2
Frequency 3
Register
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the
selection of fractional and integer-feedback configurations and the
serial interface description, see the
FemtoClock NG Ceramic 5x7
Module Programming Guide.
1 -
MFRAC
+ 0.5
-
f OUT = f XTAL
-----------
MINT
+ ----------------------------------
(1)
18
P
N
2
The four configuration registers for the
P, M (MINT & MFRAC)
and
N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
4
©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability
.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(SDATA)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
DD
+ 0.5V
10mA
10mA
15mA
49.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, V
DD
=
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
160
Units
V
mA
Table 5B. Power Supply DC Characteristics, V
DD
=
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
155
Units
V
mA
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
5
©2012 Integrated Device Technology, Inc.
