LVDS Frequency-Programmable
Crystal Oscillator
IDT8N4S271
DATA SHEET
General Description
The IDT8N4S271 is a Factory Frequency-Programmable Crystal
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock
®
NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm
x 1.55mm package.
The device can be factory programmed to any in the range from
15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and
supports a very high degree of frequency precision of 218Hz or
better. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Features
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
Factory-programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Frequency programming resolution is 218Hz and better
One 2.5V, 3.3V LVDS clock output
Output enable control (positive polarity), LVCMOS/LVTTL
compatible
RMS phase jitter @ 231.25MHz (12kHz - 20MHz):
0.48ps (typical), integer PLL feedback configuration
RMS phase jitter @ 231.25MHz (1kHz - 40MHz):
0.50ps (typical), integer PLL feedback configuration
2.5V or 3.3V supply
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) 6-pin ceramic package
Block Diagram
PFD
&
LPF
FemtoClock
®
NG
VCO
1950-2600MHz
Q
nQ
Pin Assignment
OSC
f
XTAL
2
÷P
÷N
DNU 1
OE 2
GND 3
6 V
DD
5 nQ
4 Q
÷MINT,
MFRAC
IDT8N4S271
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
25
Configuration Register (ROM)
OE
Pullup
7
IDT8N4S271CCD
JUNE 12, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N4S271 Data Sheet
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4, 5
6
Name
DNU
OE
GND
Q, nQ
V
DD
Input
Power
Output
Power
Pullup
Type
Description
Do not use (factory use only).
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Differential clock output pair. LVDS interface levels.
Power supply pin.
NOTE:
Pullup
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
5.5
50
Maximum
Units
pF
k
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state
Outputs are enabled
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
IDT8N4S271CCD
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©2012 Integrated Device Technology, Inc.
IDT8N4S271 Data Sheet
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock f
XTAL
of either
114.285MHz or 100MHz. The PLL includes the FemtoClock NG
VCO along with the Pre-divider (P), the feedback divider (M) and the
post divider (N). The
P, M,
and
N
dividers determine the output fre-
quency based on the f
XTAL
reference. The feedback divider is frac-
tional supporting a huge number of output frequencies. The
configuration of the feedback divider to integer-only values results in
an improved output phase noise characteristics at the expense of
the range of output frequencies. Internal registers are used to hold
one factory pre-set
P, M,
and
N
configuration setting. The
P, M,
and
N
frequency configuration supports an output frequency range from
15.476MHz to 866.67MHz and from 975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency f
OUT
is
calculated by:
1
MFRAC
+ 0.5
-
f OUT
=
f XTAL
------------
MINT
+ ------------------------------------
P
N
18
2
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information section in this document. For
available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the
FemtoClock
NG Ceramic 5x7 Module Programming Guide.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum
Ratings
may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those listed in the
DC
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Characteristics or AC Characteristics
is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
product reliability.
Rating
3.63V
-0.5V to V
DD
+ 0.5V
10mA
15mA
49.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD =
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
134
Maximum
3.465
160
Units
V
mA
IDT8N4S271CCD
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©2012 Integrated Device Technology, Inc.
IDT8N4S271 Data Sheet
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Table 4B. Power Supply DC Characteristics, V
DD =
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
129
Maximum
2.625
155
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristic, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
OE
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Input Low Voltage
Input High Current
Input Low Current
OE
OE
OE
Table 4D. LVDS DC Characteristics, V
DD =
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.22
Test Conditions
Minimum
247
Typical
370
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
Table 4E. LVDS DC Characteristics, V
DD =
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.21
Test Conditions
Minimum
247
Typical
360
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
IDT8N4S271CCD
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©2012 Integrated Device Technology, Inc.
IDT8N4S271 Data Sheet
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
f
I
f
S
Parameter
Output Frequency
Initial Accuracy
Temperature Stability
Measured @ 25°C
Option code = A or B
Option code = E or F
Option code = K or L
f
A
Aging
Frequency drift over 10 year life
Frequency drift over 15 year life
Option code A, B (10 year life)
f
T
tjit(cc)
tjit(per)
Total Stability
Cycle-to-Cycle Jitter; NOTE 1
RMS Period Jitter; NOTE 1
RMS Phase Jitter (Random);
Fractional PLL feedback and
f
XTAL
=100.000MHz (2xxx order
codes), NOTES 2, 3
17MHz
f
OUT
1300MHz,
Integration range: 12kHz-20MHz
500MHz
f
OUT
1300MHz,
Integration range: 12kHz-20MHz
125MHz
f
OUT
500MHz,
Integration range: 12kHz-20MHz
RMS Phase Jitter (Random);
Integer PLL feedback and
f
XTAL
=100.00MHz
(1xxx order codes),
NOTES 2, 3
17MHz
f
OUT
125MHz,
Integration range: 12kHz-20MHz
f
OUT
½156.25MHz,
Integration range: 12kHz-20MHz
f
OUT
½231.25MHz,
Integration range: 12kHz-20MHz
f
OUT
½156.25MHz,
Integration range: 1kHz-40MHz
f
OUT
½231.25MHz,
Integration range: 1kHz-40MHz
RMS Phase Jitter (Random)
Fractional PLL feedback and
f
XTAL
=114.285MHz (0xxx order
codes), NOTES 2, 3
N
(100)
N
(1k)
N
(10k)
N
(100k)
Single-side Band Phase Noise,
100Hz from Carrier
Single-side Band Phase Noise,
1kHz from Carrier
Single-side Band Phase Noise,
10kHz from Carrier
Single-side Band Phase Noise,
100kHz from Carrier
17MHz
f
OUT
1300MHz,
Integration range: 12kHz-20MHz
231.25MHz
231.25MHz
231.25MHz
231.25MHz
3
0.497
Option code E, F (10 year life)
Option code K, L (10 year life)
Test Conditions
Minimum
15.476
975
Typical
Maximum
866.67
1,300
±10
±100
±50
±20
±3
±5
±113
±63
±33
20
5
0.882
Units
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ps
ps
ps
0.232
0.250
0.275
0.242
0.476
0.275
0.504
0.322
0.450
0.405
0.311
0.680
0.359
0.700
ps
ps
ps
ps
ps
ps
ps
tjit(Ø)
0.474
0.986
ps
-88
-110
-123
-125
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
IDT8N4S271CCD
JUNE 12, 2012
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©2012 Integrated Device Technology, Inc.
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