Programmable FemtoClock
®
NG LVPECL/LVDS
Clock Generator with 8-Outputs
IDT8T49N008I
DATASHEET
General Description
The IDT8T49N008I is an eight output Clock Synthesizer with
selectable LVDS or LVPECL outputs. The IDT8T49N008I can
synthesize any one of four frequencies from a single crystal or
reference clock. The four frequencies are selected from the
Frequency Selection Table (Table 3A) and are programmed via I
2
C
interface. The four predefined frequencies are selected in the user
application by two frequency selection pins. Note the desired
programmed frequencies must be used with the corresponding
crystal or clock frequency as indicated in Table 3A.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock
®
NG PLL technology, which delivers
sub-400fs RMS phase jitter.
Features
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock NG PLL technology
Eight selectable LVPECL or LVDS outputs
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
RMS phase jitter at 156.25MHz (12kHz - 20MHz):
228fs (typical)
RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)
Full 2.5V or 3.3V power supply
I
2
C programming interface
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
Q4
nQ4
Q5
nQ5
V
CCO
Q6
nQ6
Q7
nQ7
V
EE
30 29 28 27 26 25 24 23 22 21
V
EE
SCLK
SDATA
V
EE
V
CCA
LOCK
V
EE
V
CC
CLK_SEL
V
EE
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9 10
20
19
18
17
16
15
14
13
12
11
FSEL1
V
CC
V
EE
ADDR_SEL
FSEL0
nCLK
CLK
V
EE
XTAL_OUT
XTAL_IN
IDT8T49N008I
40-Lead VFQFN
6mm x 6mm x 0.925mm package body
4.65mm x 4.65mm E-Pad
NL Package
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
1
Q0
nQ0
Q1
nQ1
V
CCO
Q2
nQ2
Q3
nQ3
V
EE
©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Block Diagram
LOCK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
Xtal
Osc
XTAL_OUT
CLK
nCLK
Pulldown
PU/PD
CLK SEL
Pulldown
XTAL_IN
0
PS
÷P[1:0]
1
Phase
Detector
+
Charge
Pump
1
÷N[6:0]
FemtoClock
®
NG
VCO
nQ3
Q4
0
nQ4
Q5
nQ5
÷M [8:1]
Q6
nQ6
Q7
VPP/FSEL
0
G_CLK/FSEL
1
SCLK
SDATA
ADDR_SEL
Pulldown
nQ7
8
8
Divider,
Pulldown
Output Type
Pullup
&
Output
Pullup
Enable
Pulldown
Selection
OUTPUT ENABLE
OUTPUT STYLE
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
2
©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 26
6, 7
8, 9
10, 13, 18,
21, 31, 34,
37, 40
11,
12
14
15
Name
Q0, nQ0
Q1, nQ1
V
CCO
Q2, nQ2
Q3, nQ3
V
EE
XTAL_IN
XTAL_OUT
CLK
nCLK
Output
Output
Power
Output
Output
Power
Type
Description
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Output supply pins.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Negative supply pins.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Crystal frequency is selected from Table 3A.
Pulldown
Pullup/
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
CC
/2.
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles and output states.
These default configurations can be overwritten after power-up via I
2
C.
LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
I
2
C Address select pin. LVCMOS/LVTTL interface levels.
Core supply pins.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Pullup
Pullup
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
I
2
C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.
Analog supply pin.
PLL Lock Indicator. LVCMOS/LVTTL interface levels.
Pulldown
Input source control pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
Input
Input
Input
16,
20
FSEL0,
FSEL1
Input
Pulldown
17
19, 38
22, 23
24, 25
27, 28
29, 30
32
33
35
36
39
ADDR_SEL
V
CC
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
SCLK
SDATA
V
CCA
LOCK
CLK_SEL
Input
Power
Output
Output
Output
Output
Input
Input/Output
Power
Output
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
3
©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Frequency Configuration
Table 3A. Frequency Configuration Examples
Output Frequencies
(MHz)
30.72
61.44
62.5
76.8
78.125
100
106.25
122.8
125
133.33
148.5
150
153.6
155.52
156.25
159.375
160
166.66
184.32
187.5
200
212.5
250
300
311.04
Input Frequency or
Crystal Frequency
(MHz)
30.72
30.72
25
30.72
25
25
26.5625
30.72
25
25
27
25
30.72
19.44
25
100
125
26.5625
20
25
30.72
61.44
25
25
26.5625
25
25
19.44
77.76
155.52
25
125
156.25
26.5625
25.78125
25
25
26.5625
30.72
30.72
122.88
153.6
19.44
25
30.72
Input Clock
Divider
P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
5
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
5
1
2
1
1
1
1
1
2
5
1
1
1
Input Clock
Prescaler
PS
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x1
x2
x2
x2
x2
x2
x1
x1
x2
x2
x2
x2
x2
x1
x1
x2
x1
x2
x2
x1
x1
x2
x2
x2
x2
x1
x2
x2
x2
x2
Feedback
Divider
M
32
32
40
40
50
40
40
32
40
48
44
42
40
64
50
50
50
36
48
40
36
36
90
40
40
40
48
64
32
32
50
40
40
36
150
90
40
40
32
40
40
40
64
50
40
Output
Divider
N
64
32
32
32
32
20
20
16
16
18
16
14
16
16
16
16
16
12
12
12
12
12
12
10
10
8
8
8
8
8
8
8
8
6
6
6
5
5
4
4
4
4
4
4
2
VCO
Frequency
(MHz)
1966.08
1966.08
2000
2457.6
2500
2000
2125
1966.08
2000
2400
2376
2100
2457.6
2488.32
2500
2500
2500
1912.5
1920
2000
2211.84
2211.84
2250
2000
2125
2000
2400
2488.32
2488.32
2488.32
2500
2500
2500
1912.5
1933.59375
2250
2000
2125
1966.08
2457.6
2457.6
2457.6
2488.32
2500
2457.6
312.5
318.75
322.265625
375
400
425
491.52
614.4
622.08
625
1228.88
NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.
NOTE: XTAL operation: f
OUT
= f
REF
* PS * M / N; CLK, nCLK input operation: f
OUT
= (f
REF
/ P) * PS * M / N.
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
4
©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Table 3B. I
2
C Register Map
Binary
Register
Address
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Register Bit
D7
M0[8]
M1[8]
M2[8]
M3[8]
unused
unused
unused
unused
unused
unused
unused
unused
LVDS_
SEL0[Q7]
LVDS_
SEL1[Q7]
LVDS_
SEL2[Q7]
LVDS_
SEL3[Q7]
OE0[Q7]
OE1[Q7]
OE2[Q7]
OE3[Q7]
reserved
unused
unused
unused
D6
M0[7]
M1[7]
M2[7]
M3[7]
N0[6]
N1[6]
N2[6]
N3[6]
BYPASS0
BYPASS1
BYPASS2
BYPASS3
LVDS_
SEL0[Q6]
LVDS_
SEL1[Q6]
LVDS_
SEL2[Q6]
LVDS_
SEL3[Q6]
OE0[Q6]
OE1[Q6]
OE2[Q6]
OE3[Q6]
reserved
unused
unused
unused
D5
M0[6]
M1[6]
M2[6]
M3[6]
N0[5]
N1[5]
N2[5]
N3[5]
PS0[1]
PS1[1]
PS2[1]
PS3[1]
LVDS_
SEL0[Q5]
LVDS_
SEL1[Q5]
LVDS_
SEL2[Q5]
LVDS_
SEL3[Q5]
OE0[Q5]
OE1[Q5]
OE2[Q5]
OE3[Q5]
reserved
unused
unused
unused
D4
M0[5]
M1[5]
M2[5]
M3[5]
N0[4]
N1[4]
N2[4]
N3[4]
PS0[0]
PS1[0]
PS2[0]
PS3[0]
LVDS_
SEL0[Q4]
LVDS_
SEL1[Q4]
LVDS_
SEL2[Q4]
LVDS_
SEL3[Q4]
OE0[Q4]
OE1[Q4]
OE2[Q4]
OE3[Q4]
reserved
unused
unused
unused
D3
M0[4]
M1[4]
M2[4]
M3[4]
N0[3]
N1[3]
N2[3]
N3[3]
P0[1]
P1[1]
P2[1]
P3[1]
LVDS_
SEL0[Q3]
LVDS_
SEL1[Q3]
LVDS_
SEL2[Q3]
LVDS_
SEL3[Q3]
OE0[Q3]
OE1[Q3]
OE2[Q3]
OE3[Q3]
reserved
unused
unused
unused
D2
M0[3]
M1[3]
M2[3]
M3[3]
N0[2]
N1[2]
N2[2]
N3[2]
P0[0]
P1[0]
P2[0]
P3[0]
LVDS_
SEL0[Q2]
LVDS_
SEL1[Q2]
LVDS_
SEL2[Q2]
LVDS_
SEL3[Q2]
OE0[Q2]
OE1[Q2]
OE2[Q2]
OE3[Q2]
reserved
unused
unused
unused
D1
M0[2]
M1[2]
M2[2]
M3[2]
N0[1]
N1[1]
N2[1]
N3[1]
CP0[1]
CP1[1]
CP2[1]
CP3[1]
LVDS_
SEL0[Q1]
LVDS_
SEL1[Q1]
LVDS_
SEL2[Q1]
LVDS_
SEL3[Q1]
OE0[Q1]
OE1[Q1]
OE2[Q1]
OE3[Q1]
unused
unused
unused
unused
D0
M0[1]
M1[1]
M2[1]
M3[1]
N0[0]
N1[0]
N2[0]
N3[0]
CP0[0]
CP1[0]
CP2[0]
CP3[0]
LVDS_
SEL0[Q0]
LVDS_
SEL1[Q0]
LVDS_
SEL2[Q0]
LVDS_
SEL3[Q0]
OE0[Q0]
OE1[Q0]
OE2[Q0]
OE3[Q0]
unused
unused
unused
unused
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
5
©2014 Integrated Device Technology, Inc.
