首页 > 器件类别 > 逻辑 > 逻辑

91857AG-LF-T

PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

器件标准:

下载文档
器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
IDT (Integrated Device Technology)
零件包装代码
TSSOP
包装说明
6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
针数
48
Reach Compliance Code
compliant
系列
91857
输入调节
DIFFERENTIAL
JESD-30 代码
R-PDSO-G48
JESD-609代码
e3
长度
12.5 mm
逻辑集成电路类型
PLL BASED CLOCK DRIVER
最大I(ol)
0.001 A
湿度敏感等级
1
功能数量
1
反相输出次数
端子数量
48
实输出次数
10
最高工作温度
70 °C
最低工作温度
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP48,.3,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
260
电源
2.5 V
认证状态
Not Qualified
Same Edge Skew-Max(tskwd)
0.1 ns
座面最大高度
1.2 mm
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
温度等级
COMMERCIAL
端子面层
Matte Tin (Sn) - annealed
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
宽度
6.1 mm
最小 fmax
220 MHz
Base Number Matches
1
文档预览
Integrated
Circuit
Systems, Inc.
ICS91857
Value SSTL_2 Clock Driver (60MHz - 220MHz)
Recommended Application:
Zero delay board fan-out memory modules
Product Description/Features:
• Meets PC3200 specification for DDRI-400 support
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
Switching Characteristics:
• CYCLE - CYCLE jitter (>100MHz):<75ps
• OUTPUT - OUTPUT skew: <100ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Functionality
INPUTS
AVDD PD#
GND
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
H
L
L
H
H
X
CLK_INT
L
H
L
H
L
H
<20MHz)
(1)
OUTPUTS
PLL State
CLK_INC CLKT CLKC FB_OUTT FB_OUTC
H
L
H
L
H
L
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
Bypassed/off
Bypassed/off
off
off
Block Diagram
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
Control
on
on
off
ICS91857
PD#
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
FB_INT
FB_INC
CLK_INC
CLK_INT
CLKT5
CLKC5
PLL
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
0494C—08/15/05
ICS91857
Pin Descriptions
PIN NUMBER
4, 11, 12, 15, 21,
28, 34, 38, 45,
PIN NAME
VDD
TYPE
PWR
PWR
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
DESCRIPTION
Power supply 2.5V up to DDR 333.
Power supply 2.6V for DDR-I at 400MHz.
Ground
Analog power supply, 2.5V up to DDR 333.
Power supply 2.6V for DDR-I at 400MHz.
A n a l o g gr o u n d .
"Tr ue" Clock of differential pair outputs.
"Complementar y" clocks of differential pair outputs.
"Complementar y" reference clock input
"True" reference clock input
"Complementar y" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" Feedback output, dedicated for external feedback. It switches at
the same frequency as the CLK. This output must be wired to FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementar y" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Power Down. LVCMOS input
1, 7, 8, 18, 24, 25,
GND
31, 41, 42, 48
16
17
AVDD
AGND
27, 29, 39, 44, 46,
CLKT(9:0)
22, 20, 10, 5, 3
26, 30, 40, 43, 47,
CLKC(9:0)
23, 19, 9, 6, 2
14
13
33
32
36
35
37
CLK_INC
CLK_INT
FB_OUTC
FB_OUTT
FB_INT
FB_INC
PD#
This PLL Clock Buffer is designed for a V
DD
of 2.5V, an AV
DD
of 2.5V and differential data input and output levels.
ICS91857
is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The
clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the 2.5-
V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV
DD
is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will
enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input
buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input
is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on,
the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INC, CLK_INT).
The PLL in the
ICS91857
clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The
ICS91857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS91857
is characterized for operation from 0°C to 70°C and will meet JEDEC Standard 82-1 and 82-1A for Registered
DDR Clock Driver.
0494C—08/15/05
2
ICS91857
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . .
-0.5V to 4.6V
GND –0.5 V to V
DD
+ 0.5 V
0°C to +70°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics for DDR200/266/333 - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage A
VDD
, V
DD
= 2.5V ± 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
Output High Current
Output Low Current
High Impedance
Output Current
Input Clamp Voltage
High-level output
voltage
SYMBOL
I
IH
I
IL
I
DD2.5
I
DDPD
I
OH
I
OL
I
OZ
V
IK
CONDITIONS
V
I
= V
DD
or GND
V
I
= V
DD
or GND
C
L
= 0pf @ 200MHz
C
L
= 0pf
V
DD
= 2.3V, V
OUT
= 1V
V
DD
= 2.3V, V
OUT
= 1.2V
V
DD
=2.7V, Vout=V
DD
or GND
V
DDQ
= 2.3V Iin = -18mA
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DDQ
= 2.3V
I
OH
=12 mA
V
I
= GND or V
DD
V
OUT
= GND or V
DD
V
DDQ
- 0.1
1.7
0.1
0.6
3
3
MIN
5
TYP
MAX
5
260
100
-18
26
-32
35
±10
-1.2
UNITS
µA
µA
mA
mA
mA
mA
mA
V
V
V
V
V
pF
pF
V
OH
Low-level output voltage
V
OL
Input Capacitance
1
Output Capacitance
1
1
C
IN
C
OUT
Guaranteed by design at 170MHz, not 100% tested in production.
0494C—08/15/05
3
ICS91857
Electrical Characteristics for DDRI-400 - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage A
VDD
, V
DD
= 2.6V ± 0.1V
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
Output High Current
Output Low Current
High Impedance
Output Current
Input Clamp Voltage
High-level output
voltage
SYMBOL
I
IH
I
IL
I
DD2.5
I
DDPD
I
OH
I
OL
I
OZ
V
IK
CONDITIONS
V
I
= V
DD
or GND
V
I
= V
DD
or GND
C
L
= 0pf @ 200MHz
C
L
= 0pf
V
DD
= 2.3V, V
OUT
= 1V
V
DD
= 2.3V, V
OUT
= 1.2V
V
DD
=2.7V, Vout=V
DD
or GND
V
DDQ
= 2.3V Iin = -18mA
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DDQ
= 2.3V
I
OH
=12 mA
V
I
= GND or V
DD
V
OUT
= GND or V
DD
V
DDQ
- 0.1
1.7
0.1
0.6
3
3
MIN
5
TYP
MAX
5
260
100
-18
26
-32
35
±10
-1.2
UNITS
µA
µA
mA
mA
mA
mA
mA
V
V
V
V
V
pF
pF
V
OH
Low-level output voltage
V
OL
Input Capacitance
1
Output Capacitance
1
1
C
IN
C
OUT
Guaranteed by design at 220MHz, not 100% tested in production.
0494C—08/15/05
4
ICS91857
Recommended Operating Condition for DDR200/266/333
(see note1)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
Low level output current
Input slew rate
Operating free-air
temperature
SYMBOL
V
DDQ
, A
VDD
V
IL
V
IH
CONDITIONS
CLKT, CLKC, FB_INC
PD#
CLKT, CLKC, FB_INC
PD#
MIN
2.3
-0.3
V
DDQ
/2 + 0.18
1.7
-0.3
V
ID
V
OX
V
IX
I
OH
I
OL
S
R
T
A
1
0
DC - CLKT, FB_INT
AC - CLKT, FB_INT
0.36
0.7
V
DDQ
/2 - 0.15
V
DDQ
/2 - 0.2
TYP
MAX
UNITS
2.7
V
V
V
DDQ
/2 - 0.18
0.7
V
V
V
DDQ
+ 0.6
V
V
DDQ
V
DDQ
+ 0.6
V
DDQ
+ 0.6
V
DDQ
/2 + 0.15
V
DDQ
/2 + 0.2
0.12
12
4
70
V
V
V
V
V
mA
mA
V/ns
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
CC
and is the
voltage at which the differential signal must be crossing.
0494C—08/15/05
5
查看更多>
参数对比
与91857AG-LF-T相近的元器件有:ICS91857AG-LF-T、ICS91857AG-LF、91857AG-LF、ICS91857AG-T、ICS91857AL-T、ICS91857ALT、ICS91857AL。描述及对比如下:
型号 91857AG-LF-T ICS91857AG-LF-T ICS91857AG-LF 91857AG-LF ICS91857AG-T ICS91857AL-T ICS91857ALT ICS91857AL
描述 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 PLL Based Clock Driver, 91857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48
是否Rohs认证 符合 符合 符合 符合 不符合 不符合 不符合 不符合
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
零件包装代码 TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
包装说明 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 TSSOP, TSSOP, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48
针数 48 48 48 48 48 48 48 48
Reach Compliance Code compliant compliant compliant compliant compliant compliant not_compliant not_compliant
系列 91857 91857 91857 91857 91857 91857 91857 91857
输入调节 DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
JESD-30 代码 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48
JESD-609代码 e3 e3 e3 e3 e0 e0 e0 e0
长度 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 9.7 mm 9.7 mm 9.7 mm
逻辑集成电路类型 PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
功能数量 1 1 1 1 1 1 1 1
端子数量 48 48 48 48 48 48 48 48
实输出次数 10 10 10 10 10 10 10 10
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度) 260 260 260 260 NOT SPECIFIED NOT SPECIFIED 225 240
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.1 ns 0.1 ns 0.1 ns 0.1 ns 0.1 ns 0.1 ns 0.1 ns 0.1 ns
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
最大供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
最小供电电压 (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
表面贴装 YES YES YES YES YES YES YES YES
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed TIN LEAD TIN LEAD Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.4 mm 0.4 mm 0.4 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30 30 NOT SPECIFIED NOT SPECIFIED 30 30
宽度 6.1 mm 6.1 mm 6.1 mm 6.1 mm 6.1 mm 4.4 mm 4.4 mm 4.4 mm
最小 fmax 220 MHz 220 MHz 220 MHz 220 MHz 220 MHz 220 MHz 220 MHz 220 MHz
是否无铅 不含铅 不含铅 不含铅 不含铅 含铅 含铅 含铅 -
最大I(ol) 0.001 A 0.001 A 0.001 A 0.001 A - - 0.001 A 0.001 A
湿度敏感等级 1 1 1 1 - - 1 1
封装等效代码 TSSOP48,.3,20 TSSOP48,.3,20 TSSOP48,.3,20 TSSOP48,.3,20 - - TSSOP48,.25,16 TSSOP48,.25,16
电源 2.5 V 2.5 V 2.5 V 2.5 V - - 2.5 V 2.5 V
Base Number Matches 1 1 1 1 1 - - -
热门器件
热门资源推荐
器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
需要登录后才可以下载。
登录取消