INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4076B
MSI
Quadruple D-type register with
3-state outputs
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
DESCRIPTION
The HEF4076B is a quadruple edge-triggered D-type
flip-flop with four data inputs (D
0
to D
3
), two active LOW
data enable inputs (ED
0
and ED
1
), a common clock input
(CP), four 3-state outputs (O
0
to O
3
), two active LOW
output enable inputs (EO
0
and EO
1
), and an overriding
asynchronous master reset input (MR).
HEF4076B
MSI
Information on D
0
to D
3
is stored in the four flip-flops on the
LOW to HIGH transition of CP if both ED
0
and ED
1
are
LOW. A HIGH on either ED
0
or ED
1
prevents the flip-flops
from changing on the LOW to HIGH transition of CP,
independent of the information on D
0
to D
3
. When both
EO
0
and EO
1
are LOW, the contents of the four flip-flops
are available at O
0
to O
3
. A HIGH on either EO
0
or
EO
1
forces O
0
to O
3
into the high impedance OFF-state. A
HIGH on MR resets all four flip-flops, independent of all
other input conditions.
Fig.2 Pinning diagram.
HEF4076BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4076BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4076BT(D): 16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
D
0
to D
3
ED
0
, ED
1
EO
0
, EO
1
CP
MR
O
0
to O
3
data inputs
data enable inputs (active LOW)
output enable inputs (active LOW)
clock input (LOW to HIGH, edge-triggered)
master reset input
data outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
HEF4076B
MSI
Fig.3 Logic diagram.
January 1995
3
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
FUNCTION TABLE
INPUTS
MR
H
L
L
L
L
L
CP
X
ED
0
X
H
X
L
L
X
ED
1
X
X
H
L
L
X
D
n
X
X
X
H
L
X
OUTPUTS
O
n
L
no change
no change
H
L
no change
Notes
HEF4076B
MSI
1. EO
0
= EO
1
= LOW
When either EO
0
or EO
1
is HIGH, the outputs are
disabled (high impedance OFF-state).
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns; see also waveforms Fig.4
V
DD
V
Propagation delays
CP
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
MR
→
O
n
HIGH to LOW
Output transition times
HIGH to LOW
10
15
5
10
15
5
10
15
5
LOW to HIGH
3-state propagation times
Output disable times
EO
n
→
O
n
HIGH
LOW
5
10
15
5
10
15
t
PLZ
t
PHZ
50
35
30
45
30
30
105
70
65
90
65
60
ns
ns
ns
ns
ns
ns
10
15
t
TLH
t
THL
t
PHL
t
PLH
t
PHL
150
60
45
160
65
45
95
40
30
60
30
20
60
30
20
305
120
85
320
130
90
190
85
65
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
123 ns
+
(0,55 ns/pF) C
L
49 ns
+
(0,23 ns/pF) C
L
37 ns
+
(0,16 ns/pF) C
L
133 ns
+
(0,55 ns/pF) C
L
54 ns
+
(0,23 ns/pF) C
L
37 ns
+
(0,16 ns/pF) C
L
68 ns
+
(0,55 ns/pF) C
L
29 ns
+
(0,23 ns/pF) C
L
22 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
January 1995
4
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
HEF4076B
MSI
TYPICAL EXTRAPOLATION
FORMULA
ns
ns
ns
ns
ns
ns
V
DD
V
Output enable times
EO
n
→
O
n
HIGH
LOW
5
10
15
5
10
15
SYMBOL
MIN.
TYP.
65
MAX.
130
55
40
120
50
35
t
PZH
30
20
60
t
PZL
25
20
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Set-up times
D
n
→
CP
5
10
15
5
ED
n
→
CP
Hold times
D
n
→
CP
10
15
5
10
15
5
ED
n
→
CP
Minimum clock
pulse width; LOW
Minimum MR pulse
width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
10
15
5
10
15
5
10
15
5
10
15
5
10
15
f
max
t
RMR
t
WMRH
t
WCPL
t
hold
t
hold
t
su
t
su
SYMBOL
MIN.
10
0
0
0
0
0
55
20
15
25
10
5
120
45
30
55
30
20
90
35
20
4
11
16
TYP.
−15
−10
−5
−50
−20
−15
30
10
10
−25
−10
−5
60
20
15
25
15
10
45
15
10
8
22
32
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
see also waveforms
Fig.4
TYPICAL EXTRAPOLATION
FORMULA
January 1995
5
