INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT138
3-to-8 line decoder/demultiplexer;
inverting
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FEATURES
•
Demultiplexing capability
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Active LOW mutually exclusive outputs
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT138 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT138
The 74HC/HCT138 decoders accept three binary
weighted address inputs (A
0
, A
1
, A
2
) and when enabled,
provide 8 mutually exclusive active LOW outputs (Y
0
to
Y
7
).
The “138” features three enable inputs: two active LOW
(E
1
and E
2
) and one active HIGH (E
3
). Every output will be
HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel
expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.
The ”138” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The ”138” is identical to the “238” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
t
PHL
/ t
PLH
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
A
n
to Y
n
E
3
to Y
n
E
n
to Y
n
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
14
3.5
67
17
19
3.5
67
ns
ns
pF
pF
HCT
UNIT
September 1993
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
PIN DESCRIPTION
PIN NO.
1, 2, 3
4, 5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
SYMBOL
A
0
to A
2
E
1
, E
2
E
3
GND
Y
0
to Y
7
V
CC
NAME AND FUNCTION
address inputs
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
outputs (active LOW)
positive supply voltage
74HC/HCT138
handbook, halfpage
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
15
14
13
12
11
10
9
7
4
5
6
E1
E2
E3
Y5
Y6
Y7
MLB312
Fig.1 Pin configuration.
Fig.2 Logic symbol.
(a)
(b)
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FUNCTION TABLE
INPUTS
E
1
H
X
X
L
L
L
L
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
E
2
X
H
X
L
L
L
L
L
L
L
L
E
3
X
X
L
H
H
H
H
H
H
H
H
A
0
X
X
X
L
H
L
H
L
H
L
H
A
1
X
X
X
L
L
H
H
L
L
H
H
A
2
X
X
X
L
L
L
L
H
H
H
H
Y
0
H
H
H
L
H
H
H
H
H
H
H
Y
1
H
H
H
H
L
H
H
H
H
H
H
Y
2
H
H
H
H
H
L
H
H
H
H
H
OUTPUTS
Y
3
H
H
H
H
H
H
L
H
H
H
H
Y
4
H
H
H
H
H
H
H
L
H
H
H
74HC/HCT138
Y
5
H
H
H
H
H
H
H
H
L
H
H
Y
6
H
H
H
H
H
H
H
H
H
L
H
Y
7
H
H
H
H
H
H
H
H
H
H
L
Fig.5 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
A
n
to Y
n
propagation delay
E
3
to Y
n
propagation delay
E
n
to Y
n
output transition
time
+25
typ.
41
15
12
47
17
14
47
17
14
19
7
6
max.
150
30
26
150
30
26
150
30
26
75
15
13
−40
to
+85
min.
max.
190
38
33
190
38
33
190
38
33
95
19
16
−40
to
+125
min.
max.
225
45
38
225
45
38
225
45
38
110
22
19
ns
UNIT
74HC/HCT138
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Figs 6 and 7
September 1993
5
