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933859120602

IC F/FAST SERIES, 9 1-BIT DRIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24, Bus Driver/Transceiver

器件类别:逻辑    逻辑   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
厂商名称
NXP(恩智浦)
零件包装代码
DIP
包装说明
DIP,
针数
24
Reach Compliance Code
unknown
系列
F/FAST
JESD-30 代码
R-PDIP-T24
长度
31.7 mm
逻辑集成电路类型
BUS DRIVER
位数
1
功能数量
9
端口数量
2
端子数量
24
最高工作温度
70 °C
最低工作温度
输出特性
3-STATE
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
传播延迟(tpd)
10 ns
认证状态
Not Qualified
座面最大高度
4.7 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
TTL
温度等级
COMMERCIAL
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
宽度
7.62 mm
文档预览
INTEGRATED CIRCUITS
74F821/822/823/824/825/826
Bus interface registers
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
74F821
74F822
74F823
74F824
74F825
74F826
10-bit bus interface register, non-inverting (3-State)
10-bit bus interface register, inverting (3-State)
9-bit bus interface register, non-inverting (3-State)
9-bit bus interface register, inverting (3-State)
8-bit bus interface register, non-inverting (3-State)
8-bit bus interface register, inverting (3-State)
DESCRIPTION
The 74F821 series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of busses
carrying parity.
The 74F821/74F822 are buffered 10-bit wide versions of the popular
74F374/74F534 functions.
The 74F822 is the inverted output version of 74F821.
The 74F823 and 74F824 are 9-bit wide buffered registers with clock
enable (CE) and master reset (MR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The 74F824 is the inverted version of 74F823.
The 74F825 and 74F826 are 8-bit buffered registers with all the
74F823/74F824 controls plus output enable (OE0, OE1, OE2) to
allow multiuser control of the interface, e.g., CS, DMA, and RD/WR.
They are ideal for uses as an output port requiring high I
OL
/I
OH
.
The 74F826 is the inverted version of 74F825.
TYPICAL
f
max
180MHz
180MHz
180MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
75mA
70mA
65mA
FEATURES
flip-flops
High speed parallel registers with positive edge-triggered D-type
High performance bus interface buffering for wide data/address
paths or busses carrying parity
High impedance PNP base inputs for reduced loading (20µA in
high and low states)
I
IL
is 20µA vs 1000µA for AM29821 series
Buffered control inputs to reduce AC effects
Ideal where high speed, light loading, or increased fan-in as
required with MOS microprocessor
Positive and negative over-shoots are clamped to ground
3-State outputs glitch free during power-up and power-down
Slim Dip 300 mil package
Broadside pinout compatible with AMD AM 29821-29826 series
Outputs sink 64mA and source 24mA
Industrial temperature range available (–40°C to +85°C) for
74F823
TYPE
74F821, 74F822
74F823, 74F824
74F825, 74F826
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F821N, N74F822N, N74F823N,
N74F824N, N74F825N, N74F826N
N74F821D, N74F822D, N74F823D,
N74F824D, N74F825D, N74F826D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F823N
I74F823D
PKG. DWG. #
24-pin plastic slim DIP (300mil)
24-pin plastic SOL
SOT222-1
SOT137-1
1996 Jan 05
2
853-1304 16195
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
Dn
74F821
74F822
CP
OE
Qn, Qn
Dn
CP
74F823
74F824
CE
MR
OE
Qn, Qn
Dn
CP
74F825
74F826
CE
MR
OE
Qn, Qn
Data inputs
Clock input
Output enable input (active low)
Data outputs
Data inputs
Clock input
Clock enable input (active low)
Master reset input (active low)
Output enable input (active low)
Data outputs
Data inputs
Clock input
Clock enable input (active low)
Master reset input (active low)
Output enable input (active low)
Data outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1200/106.7
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
1.0/3.0
1200/106.7
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
1.0/3.0
1200/106.7
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION – 74F821
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
LOGIC SYMBOL – 74F821
2
3
4
5
6
7
8
9
10
11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
1
CP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
V
CC
= Pin 24
GND = Pin 12
23
22
21
20
19
18
17
16
15
14
SF00483
SF00482
1996 Jan 05
3
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL – 74F821
1
EN1
13
G2
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
IEC/IEEE SYMBOL – 74F822
1
EN1
13
G2
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
2D
1
2D
1
SF00484
SF00487
PIN CONFIGURATION – 74F822
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
PIN CONFIGURATION – 74F823
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
MR 11
GND 12
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
13 CP
SF00485
SF00488
LOGIC SYMBOL – 74F822
2
3
4
5
6
7
8
9
10
11
LOGIC SYMBOL – 74F823
2
3
4
5
6
7
8
9
10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
13
1
CP
OE
14
11
1
CP
CE
MR
OE
D0 D1 D2 D3 D4 D5 D6 D7 D8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23
V
CC
= Pin 24
GND = Pin 12
22
21
20
19
18
17
16
15
14
V
CC
= Pin 24
GND = Pin 12
23
22
21
20
19
18
17
16
15
SF00486
SF00489
1996 Jan 05
4
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL – 74F823
1
11
14
13
EN1
IEC/IEEE SYMBOL – 74F824
1
11
EN1
R
G1
1G2
23
22
21
20
19
18
17
16
15
R
14
G1
1G2
23
22
21
20
19
18
17
16
15
13
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10
2D
1
2D
1
SF00490
SF00493
PIN CONFIGURATION – 74F824
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
MR 11
GND 12
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
13 CP
PIN CONFIGURATION – 74F825
OE0 1
OEI 2
DO 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
MR 11
GND 12
24 V
CC
23 OE2
22 QO
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
14 CE
13 CP
SF00491
SF00494
LOGIC SYMBOL – 74F824
2
3
4
5
6
7
8
9
10
LOGIC SYMBOL – 74F825
3
4
5
6
7
8
9 10
D0 D1 D2 D3 D4 D5 D6 D7 D8
13
13
14
11
1
CP
CE
MR
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
14
11
1
2
23
CP
CE
MR
OE0
OE1
OE2
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
23
V
CC
= Pin 24
GND = Pin 12
22
21
20
19
18
17
16
15
V
CC
= Pin 24
GND = Pin 12
22
21
20
19
18
17
16
15
SF00492
SF00495
1996 Jan 05
5
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