INTEGRATED CIRCUITS
74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648A
Octal transceiver/register, inverting
(3-State)
Product data
Replaces 74F646/646A/74F648/648A dated 1990 Sep 25
2003 Feb 04
Philips
Semiconductors
Philips Semiconductors
Product data
Transceivers/registers
74F646A:
Octal transceiver/register, non-inverting (3-State)
74F648A:
Octal transceiver/register, inverting (3-State)
FEATURES
74F646A/74F648A
•
Combines 74F245 and two 74F374 type functions in one chip
•
High impedance base inputs for reduced loading (70
µA
in HIGH
and LOW states)
DESCRIPTION
The 74F646A and 74F648A transceivers/registers consist of bus
transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from
the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes HIGH.
Output enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
The select pins (SAB, SBA) determine whether data is stored or
transferred through the device in real-time. The DIR determines
which bus will receive data when the OE is active LOW. In the
isolation mode (OE = HIGH), data from bus A may be stored in the
B register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
Choice of non-inverting and inverting data paths
•
Controlled ramp outputs for 74F646A/74F648A
•
3-state outputs
•
300 mil wide 24-pin slim DIP package
TYPE
74F646A, 74F648A
TYPICAL f
max
185 MHz
TYPICAL SUPPLY CURRENT (TOTAL)
105 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
24-pin plastic slim DIP (300 mil)
24-pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5 V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F646AN, N74F648AN
N74F646AD, N74F648AD
SOT222-1
SOT137-1
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0-A7, B0-B7
CPAB
CPBA
SAB
SBA
DIR
OE
A0 - A7, B0 - B7
A and B inputs
A-to-B clock input
B-to-A clock input
A-to-B select input
B-to-A select input
Data flow directional control enable input
Output enable input
A, B outputs for N74F646A/N74F648A
DESCRIPTION
74F (U.L.)
HIGH/LOW
3.5 / 0.116
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
750 / 80
LOAD VALUE
HIGH / LOW
70
µA
/ 70
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
15 mA / 48 mA
NOTE:
One (1.0) FAST unit load is defined as: 20
µA
in the HIGH state and 0.6 mA in the LOW state.
2003 Feb 04
2
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
PIN CONFIGURATION
74F646A
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
IEC/IEEE SYMBOL
74/646A
21
3
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
5
6
7
8
7
7
20
23
22
1
2
4
17 B3
16 B4
15 B5
14 B6
13 B7
5
5
1
2
1
4D
19
18
17
16
15
GND 12
SF00386
9
10
11
/
14
13
LOGIC SYMBOL
SF00388
74F646A
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7
1
2
3
23
22
21
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
OE
21
74F646A
DIR3
23
CPBA
22
SBA
1
CPAB
2
SAB
V
CC
= Pin 24
GND = Pin 12
20
19
18
17
16
15
14
13
I of 8 channels
1D
C1
SF00387
A0
4
1D
C1
20
B0
V
CC
= Pin 24
GND = Pin 12
to 7 other channels
SF00393
2003 Feb 04
3
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
PIN CONFIGURATION
74F648A
IEC/IEEE SYMBOL
74F648A
21
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
5
6
7
8
4
1
6D
1
7
7
23
22
1
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
20
3
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
5
5
1
1
2
4D
A6 10
A7 11
GND 12
19
18
17
16
15
14
13
SF00389
9
10
11
LOGIC SYMBOL
74F648A
4
5
6
7
8
9
10
11
SF00391
LOGIC DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7
1
2
3
23
22
21
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
20
19
18
17
16
15
14
13
21
OE
DIR
CPBA
SBA
CPAB
SAB
3
23
22
1
2
74F648A
1D
C1
V
CC
= Pin 24
GND = Pin 12
SF00390
A0
4
1D
C1
20
B0
to 7 other channels
SF00400
2003 Feb 04
4
Philips Semiconductors
Product data
Transceivers/registers
74F646A/74F648A
FUNCTION TABLE
INPUTS
OE
X
X
H
H
L
L
L
L
NOTES:
1. H =
2. L =
3. X =
4.
↑
=
5. * =
DIR
X
X
X
X
L
L
H
H
CPAB
↑
X
↑
H or L
X
X
X
H or L
CPBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
An
Input
Unspecified*
Input
Input
Output
Output
Input
Input
DATA I/O
Bn
Unspecified*
Input
Input
Input
Input
Input
Output
Output
OPERATING MODE
74F646A
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
74F648A
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
High-voltage level
Low-voltage level
Don’t care
LOW-to-HIGH clock transition
The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in HIGH output state
Current applied to output in LOW output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
72
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
HIGH-level input voltage
LOW-level input voltage
Input clamp current
HIGH-level output current
LOW-level output current
Operating free air temperature range
4.5
2.0
–
–
–
–
0
LIMITS
NOM
5.0
–
–
–
–
–
–
MAX
5.5
–
0.8
–18
–15
48
+70
V
V
V
mA
mA
mA
°C
UNIT
2003 Feb 04
5
