XTSC424.xxx - 0402 Extreme Temperature
Silicon Capacitor
Rev 3.1
Key features
n
Ultra High temperature up to 250°C:
w
Temperature Coeff : <±1.5%(-55 °C to +250°C)
w
Voltage <0.1 %/V
w
Negligible capacitance loss through aging
n
Unique high capacitance in EIA/0402 package
size, up to 100 nF
n
High reliability (FIT <0.017 parts / billion hours)
n
Low leakage current down to 100 pA
n
Low ESL and Low ESR
n
Suitable for lead free reflow-soldering
*Please refer
to our assembly Application Note for further recommendations
Key applications
n
250°C requirements, High temperature
applications, such as military, aerospace,
automotive and downhole industries.
High reliability applications
Replacement of X8R and C0G dielectrics
Decoupling / Filtering / Charge pump
(i.e.: pressure sensor, motor management)
Downsizing
n
n
n
n
Thanks to the unique IPDiA Silicon capacitor
technology, most of the problems encountered in
demanding applications can be solved.
EXtreme
Temperature Silicon Capacitors
are
appropriate for applications used in extreme
operating temperature range (up to
250°C).
XTSC industry leading performances allow to
propose a
100nF in 0402
with a
TC<±1.5%
over
the full -55°C/+250°C temperature range.
This technology also offers a
negligible ageing
and a stable insulation resistance, even at very
high temperature, as well as a stable capacitor
value over the full operating.
The
IPDiA
technology
features
a
capacitor
²
integration capability (up to 250nF/mm ) which
allows a capacitance value similar to X8R
dielectric, but with better electrical performances
than C0G/NP0 dielectrics.
This technology also offers
high reliability,
up to
10
times
better
than
alternative
capacitor
technologies, such as Tantalum or MLCC, and
eliminates cracking phenomena.
This Silicon based technology is RoHS compliant
and compatible with lead free reflow soldering
process.
XTSC424.xxx
Electrical specification
Capacitance value
10
15
22
33
47
68
Contact
IPDIA Sales
680 pF:
935.133.424.368
6.8 nF:
935.133.424.468
Contact
IPDIA Sales
Contact
Contact
Contact
1 pF
IPDIA Sales
IPDIA Sales
IPDIA Sales
100 pF:
150 pF:
220 pF:
10 pF
935.133.424.310 935.133.424.315 935.133.424.322
1 nF:
1.5 nF:
2.2 nF:
0.1 nF
935.133.424.410 935.133.424.415 935.133.424.422
10 nF:
15 nF:
22 nF:
1 nF
935.133.424.510 935.133.424.515 935.133.424.522
100 nF:
10 nF
935.133.424.610
Contact
Contact
IPDIA Sales
IPDIA Sales
330 pF:
470 pF:
935.133.424.333 935.133.424.347
3.3 nF:
4.7 nF:
935.133.424.433 935.133.424.447
47 nF:
33 nF:
935.133.424.547
935.133.424.533 935.133.724.547
Parameters
Capacitance range
Capacitance tolerances
Operating temperature range
Storage temperatures
Temperature coefficient
Breakdown voltage (BV)
Capacitance variation versus
RVDC
Equivalent Serial Inductor (ESL)
Equivalent Serial Resistor (ESR)
Insulation resistance
Ageing
Reliability
Capacitor height
Value
100pF to 100 nF
(**)
±15
%
(**)
-55 °C to 250 °C
- 70 °C to 265 °C
<±1.5 %, from -55 °C to +250 °C
11 VDC, 30VDC
0.1 % /V (from 0 V to RVDC)
Max 100 pH
(**)
Max 400mW
50G
W
min @ 3V,25°C
10G
W
min @ 3V,250°C
Negligible, < 0.001 % / 1000 h
FIT<0.017 parts / billion hours,
(*)
Max 400 µm
Unit
(*) Thinner thickness (as low as 100 µm thick) available, see Low Profile Silicon Capacitor product: LPSC
(**) Other values on request.
DC Voltage stability
MLCC capacitors vs. PICS
10
PICS
0
-10
Capacitance change (%)
ESL (nH) @25°C
0402 C0G(NPO) vs. PICS
1,1
1
C0G
0,9
0,8
0,7
C0G
-20
-30
X7R
-40
-50
-60
-70
-80
-90
-100
0
1
2
3
Bias voltage (V)
4
5
6
7
Y5V
ESL(nH)
0,6
0,5
0,4
0,3
0,2
PICS
0,1
0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950 1000
Capacitance (pF)
Fig.1 Capacitance change versus temperature
variation compared with alternative dielectrics
Fig.2 Capacitance change versus voltage
variation compared with alternative dielectrics
Fig.3 ESL versus capacitance value
compared with alternative dielectrics
Part Number
935.133.
B.2
Breakdown
Voltage
4 = 11V
7 = 30V
S.
Size
4 = 0402
U
Unit
0 = 10 f
1 = 0.1 p
2=1p
3 = 10 p
4 = 0.1 n
xx
i.e.: 47 nF/0402 case (XTSC type)
à
935.133.424.547
5=1n
6 = 10 n
7 = 0.1 µ
8=1µ
9 = 10 µ
Value (E6)
10
15
22
33
47
68
Termination and Outline
Termination
Lead-free nickel/solder coating
compatible with automatic soldering
technologies: reflow and manual
Typical dimensions, all dimensions in mm
Package outline
L
Typ.
Comp.
size
L
W
0402
W
1.20±0.05
0.70±0.05
Land
pattern
IPD
component
Solder
Resist
(0402 PCB footprint)
Packaging
Tape and reel, tray, waffle pack or wafer delivery
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 28
th
February 2014
Document identifier: CL431 111 615 122
IPD Capacitor Assembly Set Up
Rev 1.0
Application Note
Outline
Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging
with the following features:
Package dedicated to solve tombstoning effect of small SMD package;
Package compatible with SMD assembly;
Package without underfilling step;
Interconnect available with various optional finishing for specific assembly.
Assembly consideration
Standard pick & place equipment dedicated to WLCSP down to 400µm pitch.
Solder paste type 3 in most cases of EIA size.
Reflow has to be done with standard lead-free profile (for SAC alloys) or
according to JEDEC recommendations J-STD 020D-01.
Lead
Leadfree
Tp: 235 °C
T
L: 183 °C
Ts min: 100 °C
Ts max: 150 °C
t
L
: 60-150 s
Tp: 260 °C
T
L:
217 °C
Ts min: 150 °C
Ts max: 200 °C
t
L
: 60-150 s
Process recommendation
After soldering, no solder paste should touch the side of the capacitor die as that might results in
leakage currents due to remaining flux.
In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder
flux must be cleaned after reflow soldering step.
Notes: for a proper flux cleaning process, “rosin” flux type (R) or “water soluble” flux type (WS) is
recommended for the solder printing material. “No clean” flux (NC) solder paste is not recommended.
In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be
appropriate and the solder volume must be controlled:
- using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a
proper printing process.
- Mirroring pads would be the best recommendation
Application Note
Pad recommendation
The capacitor is compatible with generic requirements for flip chip design (IPC7094).
Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, …).
Die size and land pattern dimensions is set up according to following range :
EIA size
Dimension max(X1 x X2) mm
Typical . die thickness X3 (mm)
Typical pad size* (mm)
Typical pad separation (X4
mm)
0201
0.86x0.66
0402
1.26x0.76
0603
1.86x1.16
0805
2.26x1.46
1206
3.46x1.86
1812
4.76x3.66
0.1 or 0.4
0.15x0.40
0.3
0.30x0.50
0.4
0.40x0.90
0.8
0.50x1.20
1
0.60x1.60
2
0.90x3.40
2.7
X3
X2
X1
Top side
silicon
Typ.UBM thickness
3 to 5 µm
X4
After soldering, no solder paste should touch the side of the capacitor die as that might result in
leakage currents due to remaining flux.
Rev 1.0
2 of 3
Application Note
Manual Handling Considerations
These capacitors are designed to be mounted with a standard SMT line, using solder printing step,
pick and place machine and a final reflow soldering step. In case of manual handling and mounting
conditions, please follow below recommendations:
Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is
recommended).
Use of organic tip instead of metal tip for the nozzle.
Minimize temperature shocks (Substrate pre-heating is recommended).
No wire bonding on 0402 47nF, 0402 100nF, 1206 1 F and 1812 3,3µF
Process steps:
On substrate, form the solder meniscus on each land pattern targeting 100 µm
height after reflow (screen printing, dispensing solder paste or by wire soldering).
Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible
using a vacuum nozzle and organic tip.
Temporary place the capacitor on land pattern assuming the solder paste (Flux)
will stick and maintain the capacitor.
Reflow the assembly module with a dedicated thermal profile (see reflow
recommendation profile).
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 20
th
April 2012
Document identifier:
51单片机
