INTEGRATED CIRCUITS
DATA SHEET
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•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Feb 23
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
•
Output capability: standard
•
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (S
D
) and reset (R
D
) inputs; also complementary Q and
Q outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT74
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
15
16
76
3.5
24
15
18
18
59
3.5
29
ns
ns
ns
MHz
pF
pF
HCT
UNIT
1998 Feb 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC(T)74N
74HC(T)74D
74HCT74DB
74HCT74PW
PACKAGE
NAME
DIP14
SO14
SSOP14
TSSOP14
DESCRIPTION
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
74HC/HCT74
VERSION
SOT27-1
SOT108-1
SOT337-1
plastic shrink small outline package; 14 leads; body width 5.3 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1R
D
, 2R
D
1D, 2D
1CP, 2CP
1S
D
, 2S
D
1Q, 2Q
1Q, 2Q
GND
V
CC
NAME AND FUNCTION
asynchronous reset-direct input (active LOW)
data inputs
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Feb 23
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FUNCTION TABLE
INPUTS
S
D
L
H
L
R
D
H
L
L
CP
X
X
X
74HC/HCT74
OUTPUTS
D
X
X
X
Q
H
L
H
Q
L
H
H
INPUTS
S
D
H
H
Note
R
D
H
H
CP
↑
↑
D
L
H
OUTPUTS
Q
n+1
L
H
Q
n+1
H
L
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH CP transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
1998 Feb 23
4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
+25
−40
to
+85
−40
to
+125
min.
max.
265
53
45
300
60
51
300
60
51
110
22
19
120
24
20
120
24
20
45
9
8
90
18
15
3
3
3
4.0
20
24
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
74HC/HCT74
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
typ. max. min. max
47
17
14
50
18
14
52
19
15
19
7
6
175
35
30
200
40
34
200
40
34
75
15
13
100
20
17
100
20
17
40
8
7
75
15
13
3
3
3
4.8
24
28
5
220
44
37
250
50
43
250
50
43
95
19
16
t
PHL
/ t
PLH
propagation delay
nS
D
to nQ, nQ
propagation delay
nR
D
to nQ, nQ
output transition time
t
PHL
/ t
PLH
t
THL
/ t
TLH
t
W
clock pulse width
HIGH or LOW
80
16
14
80
16
14
30
6
5
60
12
10
3
3
3
6.0
30
35
19
7
6
19
7
6
3
1
1
6
2
2
−6
−2
−2
23
69
82
t
W
set or reset pulse width
LOW
t
rem
removal time
set or reset
t
su
set-up time
nD to nCP
t
h
hold time
nCP to nD
f
max
maximum clock pulse
frequency
1998 Feb 23
