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935254350112

IC ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48, Bus Driver/Transceiver

器件类别:逻辑    逻辑   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
NXP(恩智浦)
零件包装代码
TSSOP
包装说明
6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48
针数
48
Reach Compliance Code
unknown
系列
ALVC/VCX/A
JESD-30 代码
R-PDSO-G48
JESD-609代码
e0
长度
12.5 mm
逻辑集成电路类型
BUS TRANSCEIVER
位数
1
功能数量
16
端口数量
2
端子数量
48
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
NOT SPECIFIED
传播延迟(tpd)
3.5 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
1.2 V
标称供电电压 (Vsup)
2.4 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN LEAD
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
6.1 mm
Base Number Matches
1
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INTEGRATED CIRCUITS
DATA SHEET
74ALVCH16623
16-bit transceiver with dual enable;
3-state
Product specification
Supersedes data of 1998 Aug 31
File under Integrated Circuits, IC24
1999 Sep 20
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
FEATURES
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE™ flow-through
standard pin-out architecture
All data inputs have bus hold
circuitry
Output drive capability 50
transmission lines at 85
°C
Current drive
±24
mA at 3.0 V.
DESCRIPTION
74ALVCH16623
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOE
AB
, nOE
BA
). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling of nOE
AB
and nOE
BA
. Each output reinforces its input in
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OE
BA
should be tied to V
CC
through a pull-up resistor and OE
AB
should be tied to GND
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°C;
t
r
= t
f
= 2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I/O
C
I
C
PD
PARAMETER
propagation delay nA
n
, nB
n
to nB
n
, nA
n
input/output capacitance
input capacitance
power dissipation capacitance per buffer notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
1999 Sep 20
2
35
5
pF
pF
CONDITIONS
C
L
= 30 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
2.0
1.9
10.0
3.0
ns
ns
pF
pF
UNIT
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74ALVCH16623DGG
FUNCTION TABLE
See note 1.
INPUTS
nOE
AB
L
H
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
PINNING
PIN
1, 24
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17, 19, 20, 22, 23
25, 48
26, 27, 29, 30, 32, 33, 35, 36
37, 38, 40, 41, 43, 44, 46, 47
SYMBOL
1OE
AB
, 2OE
AB
1B
0
to 1B
7
GND
V
CC
2B
0
to 2B
7
2OE
BA
, 1OE
BA
2A
7
to 2A
0
1A
7
to 1A
0
nOE
BA
L
H
H
L
nA
n
A=B
inputs
Z
A=B
−40
to +85
°C
PINS
48
PACKAGE
TSSOP
74ALVCH16623
MATERIAL
plastic
CODE
SOT362-1
INPUTS/OUTPUTS
nB
n
inputs
B=A
Z
B=A
DESCRIPTION
output enable input (active HIGH)
data inputs/outputs
ground (0 V)
DC supply voltage
data inputs/outputs
output enable input (active LOW)
data inputs/outputs
data inputs/outputs
1999 Sep 20
3
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
fpage
1OEAB
1B0
1B1
GND
1B2
1B3
VCC
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OEBA
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 1A4
40 1A5
39 GND
38 1A6
44
1A2
1B2
43
1A3
1B3
41
1A4
1B4
40
1A5
1B5
38
1A6
1B6
37
1A7
1B7
12
11
26
2A7
2B7
23
9
27
2A6
2B6
22
8
29
2A5
2B5
20
6
30
2A4
2B4
19
5
32
2A3
2B3
17
46
1A1
1B1
3
33
2A2
2B2
16
47
1A0
1B0
2
35
2A1
2B1
14
36
2A0
2B0
13
1
1OEAB
24
2OEAB
48
1OEBA
25
2OEBA
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCC 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2OEAB 24
MNA307
16623
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 VCC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OEBA
MNA308
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1999 Sep 20
4
Philips Semiconductors
Product specification
16-bit transceiver with dual enable; 3-state
74ALVCH16623
48
handbook, halfpage
1
1EN1
1EN2
25
24
2EN1
2EN2
1
47
46
44
43
41
40
38
37
2
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
1
2
13
14
16
17
19
MNA310
handbook, halfpage
VCC
data
input
to internal circuit
20
22
23
MNA309
Fig.3 IEC logic symbol.
Fig.4 Bus hold circuit.
1999 Sep 20
5
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参数对比
与935254350112相近的元器件有:935254350118、935254340112、935254340118、74ALVCH16623DGG-T、74ALVCH16623DL、74ALVCH16623DG-T、74ALVCH16623DG。描述及对比如下:
型号 935254350112 935254350118 935254340112 935254340118 74ALVCH16623DGG-T 74ALVCH16623DL 74ALVCH16623DG-T 74ALVCH16623DG
描述 IC ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver IC ALVC/VCX/A SERIES, 16-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver
是否Rohs认证 不符合 不符合 符合 符合 不符合 符合 不符合 不符合
厂商名称 NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown
系列 ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A
JESD-30 代码 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48
逻辑集成电路类型 BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER
位数 1 1 1 1 16 16 16 16
功能数量 16 16 16 16 1 1 1 1
端口数量 2 2 2 2 2 2 2 2
端子数量 48 48 48 48 48 48 48 48
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP SOP SOP TSSOP SSOP TSSOP TSSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 260 NOT SPECIFIED NOT SPECIFIED
传播延迟(tpd) 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
标称供电电压 (Vsup) 2.4 V 2.4 V 2.4 V 2.4 V 2.4 V 2.4 V 2.4 V 2.4 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 40 NOT SPECIFIED NOT SPECIFIED
零件包装代码 TSSOP TSSOP - - TSSOP - TSSOP TSSOP
包装说明 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48 - - PLASTIC, SOT-362, TSSOP-48 - PLASTIC, SOT-362, TSSOP-48 PLASTIC, SOT-362, TSSOP-48
针数 48 48 - - 48 - 48 48
JESD-609代码 e0 e0 - - e0 - e0 e0
长度 12.5 mm 12.5 mm - - 12.5 mm 15.875 mm 12.5 mm 12.5 mm
座面最大高度 1.2 mm 1.2 mm - - 1.2 mm 2.8 mm 1.2 mm 1.2 mm
端子面层 TIN LEAD TIN LEAD - - TIN LEAD - TIN LEAD TIN LEAD
端子节距 0.5 mm 0.5 mm - - 0.5 mm 0.635 mm 0.5 mm 0.5 mm
宽度 6.1 mm 6.1 mm - - 6.1 mm 7.5 mm 6.1 mm 6.1 mm
Base Number Matches 1 1 1 1 1 1 - -
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