74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 4 — 23 November 2012
Product data sheet
1. General description
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an
output enable input (pin OE) are common to all flip-flops. The ten flip-flops store the state
of their individual D-inputs that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops are
available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE inputs does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs and outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
10-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC821AD
74LVC821ADB
74LVC821APW
74LVC821ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
DHVQFN24 plastic dual in-line compatible thermal enhanced
SOT815-1
very thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
4. Functional diagram
13
1
13
2
3
4
5
6
7
8
9
10
11
CP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE
11
1
001aaa677
C1
EN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
1D
23
22
21
20
19
18
17
16
15
14
001aaa678
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC821A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 23 November 2012
2 of 20
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
2
3
4
5
6
7
8
9
10
11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
FF0
to
FF9
3-STATE
OUTPUTS
Q0 23
Q1 22
Q2 21
Q3 20
Q4 19
Q5 18
Q6 17
Q7 16
Q8 15
Q9 14
13 CP
1 OE
001aaa679
Fig 3.
Functional diagram
74LVC821A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 23 November 2012
3 of 20
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
D0
D1
D2
D3
D4
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
CP
OE
Q0
Q1
Q2
Q3
Q4
D5
D6
D7
D8
D9
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF6
FF7
FF8
FF9
FF10
Q5
Q6
Q7
Q8
Q9
001aaa681
Fig 4.
Logic diagram
74LVC821A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 23 November 2012
4 of 20
NXP Semiconductors
74LVC821A
10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
D0
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
GND
(1)
GND 12
CP 13
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
OE
1
821A
821A
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
D8 10
D9 11
D8 10
D9 11
GND 12
001aaa676
001aaa680
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO24 and (T)SSOP24
Fig 6.
Pin configuration DHVQFN24
5.2 Pin description
Table 2.
Symbol
OE
CP
D[0:9]
Q[0:9]
GND
V
CC
Pin description
Pin
1
13
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
12
24
Description
output enable input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
3-state flip-flop output
ground (0 V)
supply voltage
74LVC821A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 23 November 2012
5 of 20
