74ALVCH16501
18-bit universal bus transceiver; 3-state
Rev. 5 — 10 July 2012
Product data sheet
1. General description
The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.
To ensure the high-impedance state during power-up or power-down, OEBA should be
tied to V
CC
through a pull-up resistor and OEAB should be tied to GND through a
pull-down resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
Current drive
24
mA at V
CC
= 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops capable of
operating in transparent, latched or clocked mode
All inputs have bus hold circuitry
Output drive capability 50
transmission lines at 85
C
3-state non-inverting outputs for bus-oriented applications
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ALVCH16501DGG
74ALVCH16501DL
40 C
to +85
C
40 C
to +85
C
Name
TSSOP56
SSOP56
Description
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
plastic shrink small outline package; 56 leads;
body width 7.5 mm
Version
SOT364-1
SOT371-1
Type number
4. Functional diagram
1
55
2
OEAB
CPAB
LEAB
EN1
2C3
C3
G2
OEBA
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
CPBA
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
1
2
55
OEAB
LEAB
CPAB
OEBA
LEBA
CPBA
27
28
30
A15
A16
A17
A0
LEBA
27
30
28
EN4
5C6
C6
G5
3
3D
4
1
1
1
6D
54
B0
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
001aal718
001aal717
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74ALVCH16501
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 10 July 2012
2 of 18
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
V
CC
data input
to internal circuit
001aal733
Fig 3.
Bus hold circuit
OEAB
CPBA
LEBA
CPAB
LEAB
OEBA
C1
A1
1D
C1
B1
1D
C1
1D
C1
1D
18 IDENTICAL CHANNELS
001aal719
Fig 4.
Logic diagram
74ALVCH16501
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 10 July 2012
3 of 18
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
74ALVCH16501
OEAB
LEAB
A0
GND
A1
A2
V
CC
A3
A4
1
2
3
4
5
6
7
8
9
56 GND
55 CPAB
54 B0
53 GND
52 B1
51 B2
50 V
CC
49 B3
48 B4
47 B5
46 GND
45 B6
44 B7
43 B8
42 B9
41 B10
40 B11
39 GND
38 B12
37 B13
36 B14
35 V
CC
34 B15
33 B16
32 GND
31 B17
30 CPBA
29 GND
001aal716
A5 10
GND 11
A6 12
A7 13
A8 14
A9 15
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
V
CC
22
A15 23
A16 24
GND 25
A17 26
OEBA 27
LEBA 28
Fig 5.
Pin configuration
5.2 Pin description
Table 2.
Symbol
OEAB
LEAB
A0 to A17
GND
V
CC
OEBA
LEBA
74ALVCH16501
Pin description
Pin
1
2
3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26
4, 11, 18, 25, 29, 32, 39, 46, 53, 56
7, 22, 35, 50
27
28
All information provided in this document is subject to legal disclaimers.
Description
output enable A-to-B input
latch enable A-to-B input
data inputs or outputs
ground (0 V)
positive supply voltage
output enable B-to-A
latch enable B-to-A
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 10 July 2012
4 of 18
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
Table 2.
Symbol
CPBA
B0 to B17
CPAB
Pin description
…continued
Pin
30
54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31
55
Description
clock input B-to-A
data inputs or outputs
clock input A-to-B
6. Functional description
6.1 Function table
Table 3.
Inputs
OEAB
L
H
H
H
H
H
H
H
H
[1]
Function table
[1]
Output
LEAB
X
H
H
CPAB
X
X
X
X
X
H or L
H or L
An
X
H
L
h
l
h
l
X
X
Bn
Z
H
L
H
L
H
L
H
L
hold data and display
clock data and display
latch data and display
disabled
transparent
Operating mode
L
L
L
L
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
Z = high-impedance OFF-state;
= HIGH-to-LOW clock transition;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
74ALVCH16501
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
Conditions
V
I
< 0 V
control inputs
data inputs
V
O
> V
CC
or V
O
< 0 V
[1]
[1]
[1]
Min
0.5
50
0.5
0.5
-
0.5
-
-
Max
+4.6
-
+4.6
V
CC
+ 0.5
50
V
CC
+ 0.5
50
100
Unit
V
mA
V
V
mA
V
mA
mA
V
O
= 0 V to V
CC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 10 July 2012
5 of 18
