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74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
Rev. 7 — 8 November 2011
Product data sheet
1. General description
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (LE) and an output enable input (OE) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but
has a different pin arrangement.
2. Features and benefits
Balanced propagation delays
All inputs have a Schmitt trigger action
Common 3-state output enable input
Functionally identical to the 74AHC373; 74AHCT373
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC573: CMOS input level
For 74AHCT573: TTL input level
ESD protection:
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC573
74AHC573D
74AHC573PW
74AHC573BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO20
TSSOP20
DHVQFN20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package no leads; 20 terminals;
body 2.5
4.5
0.85 mm
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package no leads; 20 terminals;
body 2.5
4.5
0.85 mm
SOT163-1
SOT360-1
SOT764-1
Name
Description
Version
Type number
74AHCT573
74AHCT573D
74AHCT573PW
74AHCT573BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO20
TSSOP20
DHVQFN20
SOT163-1
SOT360-1
SOT764-1
4. Functional diagram
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 LE
1 OE
mna809
Fig 1.
Functional diagram
74AHC_AHCT573
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 8 November 2011
2 of 19
NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
11
1
1
2
3
4
5
6
7
8
9
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
mna807
C1
EN1
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
4
5
6
7
8
9
3
1D
19
18
17
16
15
14
13
12
mna808
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig 4.
Logic diagram
74AHC_AHCT573
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 8 November 2011
3 of 19
NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
5. Pinning information
5.1 Pinning
74AHC573
74AHCT573
terminal 1
index area
D0
D1
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aad099
2
3
4
5
6
7
8
9
GND 10
LE 11
GND
(1)
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
D2
D3
D4
D5
D6
D7
573
1
OE
GND 10
001aal532
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO20 and TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
LE
Q0 to Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
74AHC_AHCT573
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 8 November 2011
4 of 19
