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935268676115

LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, PLASTIC, SOT-353, 5 PIN

器件类别：逻辑    逻辑   

厂商名称：NXP(恩智浦)

厂商官网：https://www.nxp.com

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参数 预览 参数对比
器件参数
参数名称
属性值
零件包装代码
SOT-353
包装说明
TSSOP,
针数
5
Reach Compliance Code
unknown
系列
LVC/LCX/Z
JESD-30 代码
R-PDSO-G5
长度
2 mm
逻辑集成电路类型
D FLIP-FLOP
位数
1
功能数量
1
端子数量
5
最高工作温度
85 °C
最低工作温度
-40 °C
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）
9.9 ns
认证状态
Not Qualified
座面最大高度
1.1 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
1.65 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
触发器类型
POSITIVE EDGE
宽度
1.25 mm
最小 fmax
200 MHz
Base Number Matches
1
文档预览
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G80
Single D-type flip-flop;
positive-edge trigger
Product specification
File under Integrated Circuits, IC24
2001 Apr 04
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FEATURES
•
Wide supply voltage range from 1.65 to 5.5 V
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• ±24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance
≤250
mA
•
Direct interface with TTL levels
•
SOT353 package.
DESCRIPTION
74LVC1G80
The 74LVC1G80 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of this device in a mixed 3.3 and 5 V
environment.
This device is fully specified for partial-power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G80 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
on the LOW-to-HIGH transition of the clock pulse.
The D input must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay CP to Q
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1
TYPICAL
3.4
2.3
2.4
1.8
5
17
UNIT
ns
ns
ns
ns
pF
pF
2001 Apr 04
2
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FUNCTION TABLE
See note 1.
INPUT
CP
↑
↑
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
X = don’t care;
D
L
H
X
74LVC1G80
OUTPUT
Q
H
L
q
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74LVC1G80GW
PINNING
PIN
1
2
3
4
5
D
CP
GND
Q
V
CC
SYMBOL
data input D
clock pulse input CP
ground (0 V)
data output Q
supply voltage
DESCRIPTION
TEMPERATURE
RANGE
−40
to +85
°C
PINS
5
PACKAGE
SC-88A
MATERIAL
plastic
CODE
SOT353
MARKING
VT
2001 Apr 04
3
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, halfpage
handbook, halfpage
D 1
CP 2
GND
3
MNA648
5 VCC
1
D
Q
4
80
4
Q
2
CP
MNA649
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
2
MNA650
4
Fig.3 IEE/IEC logic symbol.
2001 Apr 04
4
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, full pagewidth
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
MNA651
Fig.4 Logic diagram.
2001 Apr 04
5
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参数对比
与935268676115相近的元器件有：935268676118、SM11T2-18-40M-15K3JK、935268676125、935268676165。描述及对比如下：
型号 935268676115 935268676118 SM11T2-18-40M-15K3JK 935268676125 935268676165
描述 LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, PLASTIC, SOT-353, 5 PIN LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, PLASTIC, SOT-353, 5 PIN Parallel - 3Rd Overtone Quartz Crystal, 40MHz Nom, ROHS COMPLIANT, MINIATURE, SMD, 2 PIN IC LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, PLASTIC, SOT-353, 5 PIN, FF/Latch IC LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5, PLASTIC, SOT-353, 5 PIN, FF/Latch
包装说明 TSSOP, TSSOP, ROHS COMPLIANT, MINIATURE, SMD, 2 PIN PLASTIC, SOT-353, 5 PIN TSSOP,
Reach Compliance Code unknown unknown unknown unknown compliant
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -30 °C -40 °C -40 °C
表面贴装 YES YES YES YES YES
零件包装代码 SOT-353 SOT-353 - SOT-353 SOT-353
针数 5 5 - 5 5
系列 LVC/LCX/Z LVC/LCX/Z - LVC/LCX/Z LVC/LCX/Z
JESD-30 代码 R-PDSO-G5 R-PDSO-G5 - R-PDSO-G5 R-PDSO-G5
长度 2 mm 2 mm - 2 mm 2 mm
逻辑集成电路类型 D FLIP-FLOP D FLIP-FLOP - D FLIP-FLOP D FLIP-FLOP
位数 1 1 - 1 1
功能数量 1 1 - 1 1
端子数量 5 5 - 5 5
输出极性 INVERTED INVERTED - INVERTED INVERTED
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP - TSSOP TSSOP
封装形状 RECTANGULAR RECTANGULAR - RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd） 9.9 ns 9.9 ns - 9.9 ns 9.9 ns
认证状态 Not Qualified Not Qualified - Not Qualified Not Qualified
座面最大高度 1.1 mm 1.1 mm - 1.1 mm 1.1 mm
最大供电电压 (Vsup) 5.5 V 5.5 V - 5.5 V 5.5 V
最小供电电压 (Vsup) 1.65 V 1.65 V - 1.65 V 1.65 V
标称供电电压 (Vsup) 1.8 V 1.8 V - 1.8 V 1.8 V
技术 CMOS CMOS - CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL - INDUSTRIAL INDUSTRIAL
端子形式 GULL WING GULL WING - GULL WING GULL WING
端子节距 0.65 mm 0.65 mm - 0.65 mm 0.65 mm
端子位置 DUAL DUAL - DUAL DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE - POSITIVE EDGE POSITIVE EDGE
宽度 1.25 mm 1.25 mm - 1.25 mm 1.25 mm
最小 fmax 200 MHz 200 MHz - 200 MHz 200 MHz
厂商名称 - NXP(恩智浦) - NXP(恩智浦) NXP(恩智浦)
是否Rohs认证 - - 符合 符合 符合
JESD-609代码 - - e4 e3 e3
端子面层 - - Gold (Au) - with Nickel (Ni) barrier PURE TIN TIN
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器件捷径:
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