INTEGRATED CIRCUITS
PCA9548
8-channel I
2
C switch with reset
Product data
File under Inegrated Circuits — ICL03
2002 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product data
8-channel I
2
C switch with reset
PCA9548
PIN CONFIGURATION
A0 1
A1 2
RESET 3
SD 4
SC0 5
SD1 6
24 V
DD
23 SDA
22 SCL
21 A2
20 SC7
19 SD7
18 SC6
17 SD6
16 SC5
15 SD5
14 SC4
13 SD4
FEATURES
•
1-of-8 bi-directional translating switches
•
I
2
C interface logic; compatible with SMBus standards
•
Active Low Reset Input
•
3 address pins allowing up to 8 devices on the I
2
C bus
•
Channel selection via I
2
C bus, in any combination
•
Power up with all switch channels deselected
•
Low Rds
ON
switches
•
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
•
No glitch on power-up
•
Supports hot insertion
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
5 V tolerant Inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latchup testing is done to JESDEC Standard JESD78 which
•
Package Offer: SO24, TSSOP24
DESCRIPTION
The PCA9548 is a octal bi-directional translating switch controlled
by the I
2
C bus. The SCL/SDA upstream pair fans out to eight
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9548 to recover from a
situation where one of the downstream I
2
C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9548. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
exceeds 100 mA
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
5 V buses
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SC1 7
SD2 8
SC2 9
SD3 10
SC3 11
V
SS
12
SW00361
Figure 1. Pin configuration
PIN DESCRIPTION
SYMBOL
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
V
SS
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
SCL
SDA
V
DD
FUNCTION
Address input 0
Address input 1
Active LOW reset input
Serial data output 0
Serial clock output 1
Serial data output 1
Serial clock output 2
Serial data output 2
Serial clock output 3
Serial data output 3
Serial clock output 4
Supply ground
Serial data output 4
Serial clock output 5
Serial data output 5
Serial clock output 6
Serial data output 6
Serial clock output 7
Serial data output 7
Serial clock output 8
Address input 2
Serial clock line
Serial data line
Supply voltage
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
PCA9548D
DRAWING NUMBER
SOT137-1
SOT355-1
24-Pin Plastic TSSOP
–40 to +85
°C
PCA9548PW
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Feb 19
2
853-2318 27757
Philips Semiconductors
Product data
8-channel I
2
C switch with reset
PCA9548
BLOCK DIAGRAM
PCA9548
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
V
SS
SWITCH CONTROL LOGIC
V
DD
RESET
RESET
CIRCUIT
SCL
INPUT
FILTER
I
2
C-BUS
CONTROL
A0
A1
A2
SDA
SW00371
Figure 2. Block diagram
2002 Feb 19
3
Philips Semiconductors
Product data
8-channel I
2
C switch with reset
PCA9548
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9548 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
1
1
1
0
A2
A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW00915
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9548, which will be stored
in the control register. If multiple bytes are received by the
PCA9548, it will save the last byte received. This register can be
written and read via the I
2
C bus.
CHANNEL SELECTION BITS
(READ/WRITE)
7
B7
6
B6
5
B5
4
B4
3
B3
2
B2
1
B1
0
B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
Channel 0
0
disabled
X
X
X
X
X
X
X
Channel 0
1
enabled
Channel 1
0
disabled
X
X
X
X
X
X
X
Channel 1
1
enabled
Channel 2
0
disabled
X
X
X
X
X
X
X
Channel 2
1
enabled
Channel 3
0
disabled
X
X
X
X
X
X
X
Channel 3
1
enabled
Channel 4
0
disabled
X
X
X
X
X
X
X
Channel 4
1
enabled
Channel 5
0
disabled
X
X
X
X
X
X
X
Channel 5
1
enabled
Channel 6
0
disabled
X
X
X
X
X
X
X
Channel 6
1
enabled
Channel 7
0
disabled
X
X
X
X
X
X
X
Channel 7
1
enabled
NOTE:
Several channels can be enabled at the same time.
Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,
means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,
3, and 2 are enabled.
Care should be taken not to exceed the maximum bus capacitance.
SW00932
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9548 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
Figure 4. Control register
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9548 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
2
C bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9548 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9548 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
2002 Feb 19
4
Philips Semiconductors
Product data
8-channel I
2
C switch with reset
PCA9548
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9548 are constructed such that
the V
DD
voltage can be used to limit the maximum voltage that will
be passed from one I
2
C bus to another.
V
pass
vs. V
DD
5.0
4.5
MAXIMUM
4.0
TYPICAL
3.5
V
pass
3.0
2.5
2.0
1.5
1.0
2.0
2.5
3.0
3.5
4.0
V
DD
4.5
5.0
5.5
MINIMUM
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the PCA9548 is only tested at the points
specified in the DC Characteristics section of this datasheet). In
order for the PCA9548 to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V
pass
(max.) will be at 2.7 V when the
PCA9548 supply voltage is 3.5 V or lower so the PCA9548 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262
PCA954X
family of I
2
C/SMBus multiplexers and switches.
SW00820
Figure 5. V
pass
voltage vs. V
DD
2002 Feb 19
5
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