INTEGRATED CIRCUITS
DATA SHEET
74LVCH32373A
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
Product specification
Supersedes data of 1999 Nov 24
2004 May 19
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 V to 3.6 V
•
CMOS low power consumption
•
MULTIBYTE flow-trough standard pin-out architecture
•
Low inductance multiple power and ground pins for
minimum noise and ground bounce
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
All data inputs have bushold
•
Complies with JEDEC standard JESD8-B/JESD36
•
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
•
Packaged in plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 V or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 V and 5 V environment.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
PARAMETER
propagation delay nDn to nQn
propagation delay nLE to nQn
3-state output enable time nOE to nQn
3-state output disable time nOE to nQn
input capacitance
power dissipation per latch
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
2004 May 19
2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
74LVCH32373A
The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One latch enable
input (nLE) and one output enable input (nOE) are
provided for each octal. Inputs can be driven from either
3.3 V or 5 V devices.
The 74LVCH32373A consists of 4 sections of eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.
When input nLE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH32373A bushold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
TYPICAL
3.0
3.4
3.5
3.9
5.0
15
11
ns
ns
ns
ns
pF
pF
pF
UNIT
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
C
L
= output load capacity in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODE
nOE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74LVCH32373AEC
PINNING
BALL
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
SYMBOL
1Q1
1Q0
1OE
1LE
1D0
1D1
1Q3
1Q2
GND
GND
DESCRIPTION
data output
data output
output enable input (active LOW)
latch enable input (active HIGH)
data input
data input
data output
data output
ground (0 V)
ground (0 V)
3
−40 °C
to +85
°C
PINS
96
PACKAGE
LFBGA96
L
L
L
L
H
H
nLE
H
H
L
L
L
L
nDn
L
H
l
h
l
h
74LVCH32373A
INTERNAL
LATCH
L
H
L
H
L
H
OUTPUT
nQn
L
H
L
H
Z
Z
MATERIAL
plastic
CODE
SOT536-1
BALL
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
SYMBOL
1D2
1D3
1Q5
1Q4
V
CC
V
CC
1D4
1D5
1Q7
1Q6
GND
data input
data input
DESCRIPTION
data output
data output
supply voltage
supply voltage
data input
data input
data output
data output
ground (0 V)
2004 May 19
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
BALL
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
J1
J2
J3
J4
J5
J6
K1
K2
K3
K4
K5
K6
L1
L2
SYMBOL
GND
1D6
1D7
2Q1
2Q0
GND
GND
2D0
2D1
2Q3
2Q2
V
CC
V
CC
2D2
2D3
2Q5
2Q4
GND
GND
2D4
2D5
2Q6
2Q7
2OE
2LE
2D7
2D6
3Q1
3Q0
3OE
3LE
3D0
3D1
3Q3
3Q2
GND
GND
3D2
3D3
3Q5
3Q4
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
supply voltage
supply voltage
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
output enable input (active LOW)
latch enable input (active HIGH)
data input
data input
data output
data output
output enable input (active LOW)
latch enable input (active HIGH)
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
4
DESCRIPTION
ground (0 V)
BALL
L3
L4
L5
L6
M1
M2
M3
M4
M5
M6
N1
N2
N3
N4
N5
N6
P1
P2
P3
P4
P5
P6
R1
R2
R3
R4
R5
R6
T1
T2
T3
T4
T5
T6
SYMBOL
V
CC
V
CC
3D4
3D5
3Q7
3Q6
GND
GND
3D6
3D7
4Q1
4Q0
GND
GND
4D0
4D1
4Q3
4Q2
V
CC
V
CC
4D2
4D3
4Q5
4Q4
GND
GND
4D4
4D5
4Q6
4Q7
4OE
4LE
4D7
4D6
74LVCH32373A
DESCRIPTION
supply voltage
supply voltage
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
supply voltage
supply voltage
data input
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
output enable input (active LOW)
latch enable input (active HIGH)
data input
data input
2004 May 19
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
mna492
6
5
4
3
2
1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
1LE GND V
CC
GND GND V
CC
GND 2LE
3LE GND V
CC
GND GND V
CC
GND 4LE
1OE GND V
CC
GND GND V
CC
GND 2OE 3OE GND V
CC
GND GND V
CC
GND 4OE
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH 1
LATCH 9
LE
LE
LE
LE
1LE
1OE
to 7 other channels
2LE
2OE
to 7 other channels
3D0
D
Q
3Q0
4D0
D
Q
4Q0
LATCH 17
LATCH 25
LE
LE
LE
LE
3LE
3OE
to 7 other channels
4LE
4OE
to 7 other channels
mna493
Fig.2 Logic symbol.
2004 May 19
5
