LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 7.1 — 16 October 2013
Product data sheet
1. General description
The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation that combines the microcontroller with up to 512 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.
They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed
device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels
(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three
I
2
C-bus interfaces, and an I
2
S-bus interface. This blend of serial communications
interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB
SRAM for Ethernet, 8 kB SRAM for USB and general purpose use, together with 2 kB
battery powered SRAM make these devices very well suited for communication gateways
and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one
PWM unit, a CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up
to 12 edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB SRAM for general purpose DMA use also accessible by the USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
2
S port, and the Secure Digital/MultiMediaCard (SD/MMC) card
port, as well as for memory-to-memory transfers.
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
Serial interfaces:
Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB.
USB 2.0 full-speed device with on-chip PHY and associated DMA controller
(LPC2364/66/68 only).
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels (LPC2364/66/68 only).
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA
controller.
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
Other peripherals:
SD/MMC memory card interface (LPC2367/68 only).
70 general purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 6 pins.
10-bit DAC.
Four general purpose timers/counters with a total of 8 capture inputs and 10
compare outputs. Each timer block has an external count input.
One PWM/timer block with support for three-phase motor control. The PWM has
two external count inputs.
Real-Time Clock (RTC) with separate power pin, clock source can be the RTC
oscillator or the APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0
and Port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7.1 — 16 October 2013
2 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
Boundary scan for simplified board testing is available in LPC2364FET100 and
LPC2368FET100 (TFBGA package).
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
Industrial control
Medical systems
Protocol converter
Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC2364FBD100
LPC2364HBD100
LPC2364FET100
LPC2365FBD100
LPC2366FBD100
LPC2367FBD100
LPC2368FBD100
LPC2368FET100
LQFP100
LQFP100
TFBGA100
LQFP100
LQFP100
LQFP100
LQFP100
TFBGA100
Description
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
Version
SOT407-1
SOT407-1
SOT407-1
SOT407-1
SOT407-1
SOT407-1
Type number
plastic thin fine-pitch ball grid array package; 100 balls; body 9
9
0.7 mm SOT926-1
plastic thin fine-pitch ball grid array package; 100 balls; body 9
9
0.7 mm SOT926-1
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7.1 — 16 October 2013
3 of 69
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Product data sheet
Rev. 7.1 — 16 October 2013
4 of 69
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
NXP Semiconductors
4.1 Ordering options
Table 2.
Ordering options
Flash
SRAM (kB)
(kB) Local Ethernet GP/USB RTC
bus
buffers
128
128
256
256
512
512
512
8
8
8
32
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
Total
Ethernet USB
SD/MMC GP DMA
Channels
Temp range
device +
CAN ADC DAC
4 kB
FIFO
RMII
RMII
RMII
RMII
RMII
RMII
RMII
RMII
yes
yes
yes
no
yes
no
yes
yes
no
no
no
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
2
2
2
-
2
-
2
2
6
6
6
6
6
6
6
6
1
1
1
1
1
1
1
1
40 C
to +85
C
40 C
to +125
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Type number
LPC2364FBD100
LPC2364FET100
LPC2365FBD100
LPC2366FBD100
LPC2367FBD100
LPC2368FBD100
LPC2368FET100
34
34
34
58
58
58
58
58
LPC2364HBD100 128
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
5. Block diagram
XTAL1
XTAL2
V
DDA
TMS TDI
trace signals
TRST
TCK TDO
EXTIN0
RESET
V
DD(3V3)
VREF
V
SSA
, V
SS
V
DD(DCDC)(3V3)
LPC2364/65/66/67/68
P0, P1, P2,
P3, P4
HIGH-SPEED
GPI/O
70 PINS
TOTAL
8/32 kB
SRAM
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
128/256/
512 kB
FLASH
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
INTERNAL
CONTROLLERS
SRAM FLASH
ARM7TDMI-S
VECTORED
INTERRUPT
CONTROLLER
AHB
BRIDGE
8 kB
SRAM
AHB1
AHB2
AHB
BRIDGE
RMII(8)
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
USB WITH
4 kB RAM
AND DMA
(2)
V
BUS
USB_D+, USB_D−
USB_CONNECT
USB_UP_LED
GP DMA
CONTROLLER
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
CAN1, CAN2
(2)
I
2
C0, I
2
C1, I
2
C2
002aac566
EINT3 to EINT0
P0, P2
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2,
2
×
MAT0/MAT1/
MAT3
6
×
PWM1
2
×
PCAP1
P0, P1
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I
2
S INTERFACE
PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O
52 PINS TOTAL
SSP1 INTERFACE
6
×
AD0
A/D CONVERTER
SD/MMC CARD
INTERFACE
(1)
AOUT
D/A CONVERTER
UART0, UART2, UART3
VBAT
power domain 2
power domain 2
RTCX1
RTCX2
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
UART1
WATCHDOG TIMER
SYSTEM CONTROL
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
(1) LPC2367/68 only.
(2) LPC2364/66/68 only.
Fig 1.
LPC2364/65/66/67/68 block diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
LPC2364_65_66_67_68
Product data sheet
Rev. 7.1 — 16 October 2013
5 of 69
