PCF8533
Universal LCD driver for low multiplex rates
Rev. 03 — 24 April 2008
Product data sheet
1. General description
The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 80 segments and can easily be cascaded
for larger LCD applications. The PCF8533 is compatible with most
microprocessors/microcontrollers and communicates via a two-line bidirectional I
2
C-bus.
Communication overheads are minimized by a display RAM with auto-incremental
addressing, by hardware subaddressing and by display memory switching (static and
duplex drive modes).
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Single-chip LCD controller/driver
Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
Selectable display bias configuration: static,
1
⁄
2
or
1
⁄
3
Internal LCD bias generation with voltage-follower buffers
80 segment drives: up to forty 8-segment numeric characters; up to twenty one
15-segment alphanumeric characters; or any graphics of up to 320 elements
80
×
4 bit RAM for display data storage
Auto-incremental display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide LCD supply range: from 2.5 V for low-threshold LCDs, up to 6.5 V for guest-host
LCDs and high-threshold (automobile) twisted nematic LCDs
Low power consumption
400 kHz I
2
C-bus interface
TTL/CMOS compatible
Compatible with 4-bit, 8-bit or 16-bit microprocessors or microcontrollers
May be cascaded for large LCD applications (up to 5120 segments possible)
No external components
Compatible with Chip-On-Glass (COG) technology
Manufactured using silicon gate CMOS process
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Package
Name
PCF8533U
-
Description
chip with bumps in tray
Version
-
Type number
4. Block diagram
BP0 BP1 BP2 BP3
S0 to S79
80
V
LCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY REGISTER
DISPLAY
CONTROL
OUTPUT BANK SELECT
AND BLINK CONTROL
V
SS
LCD BIAS
GENERATOR
PCF8533
CLK
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
DISPLAY
RAM
OSC
OSCILLATOR
POWER-ON
RESET
COMMAND
DECODE
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
SCL
SDA
INPUT
FILTERS
I
2
C-BUS
CONTROLLER
SUBADDRESS
COUNTER
SA0
SDAACK
V
DD
A0
A1
A2
mgl743
Fig 1.
Block diagram of PCF8533
PCF8533_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 24 April 2008
2 of 38
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
5. Pinning information
5.1 Pinning
S12
D4
D3
S11
D1
D2
mgl759
D6
D5
S67
V
DD
SDAACK
SYNC
V
LCD
S79
BP3
BP1
SDA
CLK
OSC
SCL
SA0
BP2
BP0
S0
S1
S2
V
SS
.
.
.
.
.
.
PCF8533
y
x
0,0
D7
D8
S68
A0
A1
A2
.
.
.
.
.
.
.
.
.
.
.
.
The positions of the bonding pads are not to scale.
Fig 2.
Bonding pad locations for PCF8533 (bottom view)
REF
REF
C2
C1
F
REF
mgl756
The approximate positions of the alignment marks are shown in
Figure 2.
Fig 3.
Table 2.
Pad
1
2 and 3
4 and 5
6
7
8
9
Alignment marks
Pad allocation table
Symbol
SDAACK
SDA
SCL
CLK
V
DD
SYNC
OSC
A0, A1 and A2
© NXP B.V. 2008. All rights reserved.
10, 11 and 12
PCF8533_3
Product data sheet
Rev. 03 — 24 April 2008
3 of 38
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
Pad allocation table
…continued
Symbol
SA0
V
SS
V
LCD
BP0, BP1, BP2 and BP3
S0 to S79
Alignment mark locations
X (µm)
2300.5
−2320.5
−2208.3
Bonding pad dimensions
Size
Fab 1
[1]
Fab 2
[2]
µm
µm
5.28
1.40
mm
mm
90
×
50
×
17.5 (± 3)
381
5.40
1.51
Unit
Y (µm)
55.0
107.0
−165.4
Table 2.
Pad
13
14
15
17, 99, 16 and 98
18 to 97
Table 3.
Symbol
C1
C2
F
Table 4.
Pad
Gold bump dimensions
Wafer thickness (excluding bumps)
Die size L (length) X-direction in
Figure 2
Die size W (width) Y-direction in
Figure 2
[1]
[2]
Fabrication 1 identification starts with nnnnnn, where n represents a number between 0 and 9.
Fabrication 2 identification starts with AXnnnn, where X represents a letter and n represents a number
between 0 and 9.
Table 5.
Top right
X (µm)
2695.00
Chip corners (pre-sawing)
Bottom left
Y (µm)
750.00
X (µm)
−2695.00
Y (µm)
−750.00
5.2 Pin description
Table 6.
Bonding pad description
All x/y coordinates represent the position of the centre of each pad with respect to the center
(x/y = 0) of the chip; see
Figure 2.
Symbol
SDAACK
SDA
SDA
SCL
SCL
CLK
V
DD
SYNC
Pad
1
2
3
4
5
6
7
8
X (µm)
−839.20
−759.20
−599.20
−519.20
−414.80
−284.80
4.20
Y (µm)
[1]
[1]
[1]
Description
I
2
C-bus acknowledge output
I
2
C-bus serial data input
I
2
C-bus serial data input
I
2
C-bus serial clock input
I
2
C-bus serial clock input
external clock input/output
supply voltage
cascade synchronization input/output
−1079.20 −594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
PCF8533_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 24 April 2008
4 of 38
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
Table 6.
Bonding pad description
…continued
All x/y coordinates represent the position of the centre of each pad with respect to the center
(x/y = 0) of the chip; see
Figure 2.
Symbol
OSC
A0
A1
A2
SA0
V
SS
V
LCD
BP2
BP0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
PCF8533_3
Pad
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
X (µm)
119.20
249.20
379.20
581.20
711.20
841.20
1099.60
1277.60
1357.60
1437.60
1517.60
1597.60
1677.60
1757.60
1837.60
1917.60
1997.60
2077.60
2157.60
2237.60
2317.60
2357.60
2277.60
2197.60
2117.60
2037.60
1957.60
1877.60
1797.60
1717.60
1637.60
1557.60
1477.60
1317.60
1237.60
1157.60
1077.60
997.60
917.60
Y (µm)
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
−594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
594.40
Description
internal oscillator input and output
subaddress input
subaddress input
subaddress input
I
2
C-bus slave address input; bit 0
logic ground
LCD supply voltage
LCD backplane output
LCD backplane output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
LCD segment output
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 24 April 2008
5 of 38
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