74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 2 — 3 December 2010
Product data sheet
1. General description
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and
V
CC(B)
can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to V
CC(A)
and pins nBn are referenced to
V
CC(B)
. A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
200 Mbit/s ( 1.1 V to 3.3 V translation)
200 Mbit/s ( 1.1 V to 2.5 V translation)
200 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVCH4T245D
40 C
to +125
C
SO16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT763-1
Type number
74AVCH4T245PW
40 C
to +125
C
74AVCH4T245BQ
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
XQFN16
plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80
2.60
0.50 mm
74AVCH4T245GU
40 C
to +125
C
SOT1161-1
4. Marking
Table 2.
Marking codes
Marking code
74AVCH4T245D
CH4T245
H4T245
K4
Type number
74AVCH4T245D
74AVCH4T245PW
74AVCH4T245BQ
74AVCH4T245GU
74AVCH4T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 3 December 2010
2 of 29
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
5. Functional diagram
13
1B1
V
CC(A)
V
CC(B)
12
1B2
11
2B1
10
2B2
15
1OE
2OE
14
2
1DIR
2DIR
3
1A1
4
5
1A2
6
2A1
7
2A2
001aak280
Pin numbers are shown for SO16, TSSOP16 and DHVQFN16 packages only.
Fig 1.
Logic symbol
DIR
OE
A1
B1
A2
B2
V
CC(A)
V
CC(B)
001aak281
Fig 2.
Logic diagram (one 2-bit transceiver)
74AVCH4T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 3 December 2010
3 of 29
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
6. Pinning information
6.1 Pinning
74AVCH4T245
V
CC(A)
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
1
2
3
4
5
6
7
8
001aak288
16 V
CC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9
GND
V
CC(A)
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
1
2
3
4
5
6
7
8
001aak287
74AVCH4T245
16 V
CC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9
GND
Fig 3.
Pin configuration SOT109-1 (SO16)
Fig 4.
Pin configuration SOT403-1 (TSSOP16)
74AVCH4T245
V
CC(A)
terminal 1
index area
1DIR
2DIR
1A1
1A2
2A1
2A2
2
3
4
5
6
7
8
9
GND
GND
GND
(1)
16 V
CC(B)
74AVCH4T245
16 2OE
15 1B1
14 1B2
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
V
CC(B)
2
V
CC(A)
3
001aak289
1
terminal 1
index area
1OE 1
13 2B1
12 2B2
11 GND
10 GND
9 2A2
2A1 8
001aan189
© NXP B.V. 2010. All rights reserved.
1DIR 4
Transparent top view
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
2DIR 5
1A1 6
Transparent top view
Fig 5.
Pin configuration SOT763-1 (DHVQFN16)
Fig 6.
Pin configuration SOT1161-1 (XQFN16)
74AVCH4T245
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 2 — 3 December 2010
1A2 7
4 of 29
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT109-1, SOT403-1
and SOT763-1
V
CC(A)
1DIR, 2DIR
1A1, 1A2
2A1, 2A2
GND
[1]
2B2, 2B1
1B2, 1B1
2OE, 1OE
V
CC(B)
[1]
Description
SOT1161-1
3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 1
2
supply voltage A (nAn, nOE and nDIR inputs are
referenced to V
CC(A)
)
direction control
data input or output
data input or output
ground (0 V)
data input or output
data input or output
output enable input (active LOW)
supply voltage B (nBn inputs are referenced to V
CC(B)
)
1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16
All GND pins must be connected to ground (0 V).
7. Functional description
Table 4.
Function table
[1]
Input
nOE
[2]
L
L
H
X
nDIR
[2]
L
H
X
X
Input/output
[3]
nAn
[2]
nAn = nBn
input
Z
Z
nBn
[2]
input
nBn = nAn
Z
Z
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The nAn, nDIR and nOE input circuit is referenced to V
CC(A)
; The nBn input circuit is referenced to V
CC(B)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
74AVCH4T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 3 December 2010
5 of 29
嵌入式系统
