PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
with interrupt output, reset, and configuration registers
Rev. 3 — 18 September 2013
Product data sheet
1. General description
The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I
2
C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide V
DD
range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL6408A: V
DD(I2C-bus)
and V
DD(P)
. V
DD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the V
DD(P)
provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCAL6408A is provided through V
DD(I2C-bus)
.
V
DD(I2C-bus)
should be connected to the V
DD
of the external SCL/SDA lines. This indicates
the V
DD
level of the I
2
C-bus to the PCAL6408A, while the voltage level on Port P of the
PCAL6408A is determined by the V
DD(P)
.
The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output,
and Polarity Inversion registers and additionally, the PCAL6408A has Agile I/O, which are
additional features specifically designed to enhance the I/O. These additional features
are: programmable output drive strength, latchable inputs, programmable
pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable
open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the
PCA6408A, however, the PCAL6408A powers up with all I/O interrupts masked. This
mask default allows for a board bring-up free of spurious interrupts at power-up.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete
components.
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
The system master can reset the PCAL6408A in the event of a time-out or other improper
operation by asserting a LOW in the RESET input. The power-on reset puts the registers
in their default state and initializes the I
2
C-bus/SMBus state machine. The RESET pin
causes the same reset/initialization to occur without de-powering the part.
The PCAL6408A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the PCAL6408A can
remain a simple slave device. The input latch feature holds or latches the input pin state
and keeps the logic values that created the interrupt until the master can service the
interrupt. This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I
2
C-bus address
and allow up to two devices to share the same I
2
C-bus or SMBus.
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Allows bidirectional voltage-level translation and GPIO expansion between:
1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
Low standby current consumption of 1
A
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.18 V (typical) at 1.8 V
V
hys
= 0.25 V (typical) at 2.5 V
V
hys
= 0.33 V (typical) at 3.3 V
V
hys
= 0.5 V (typical) at 5 V
5 V tolerant I/O ports
Active LOW reset input (RESET)
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I
2
C-bus
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Noise filter on SCL/SDA inputs
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD 78, Class II
PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
2 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
ESD protection exceeds JESD 22
2000 V Human-Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: HVQFN16, TSSOP16, XQFN16,
XFBGA16 (1.6 mm
1.6 mm
0.5 mm)
2.1 Agile I/O features
Software backward compatible with PCA6408A with interrupts disabled at power-up
Pin-to-pin drop-in replacement for PCA6408A
Output port configuration: bank selectable push-pull or open-drain output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
Output drive strength: four programmable drive strengths to reduce rise and fall
times in low-capacitance applications
Input latch: Input Port register values changes are kept until the Input Port register
is read
Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
Pull-up/pull-down selection: 100 k pull-up/pull-down resistor selection
Interrupt mask: mask prevents the generation of the interrupt when input changes
state to prevent spurious interrupts
3. Ordering information
Table 1.
Ordering information
Topside
marking
L8A
Package
Name
HVQFN16
TSSOP16
XQFN16
XFBGA16
Description
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic, extremely thin quad flat package; no leads; 16 terminals;
body 1.80
2.60
0.50 mm
Version
SOT758-1
SOT403-1
SOT1161-1
Type number
PCAL6408ABS
PCAL6408APW PL6408A
PCAL6408AHK
PCAL6408AEX
L8
L8
plastic, extremely thin fine-pitch ball grid array package; 16 balls; SOT1354-1
body 1.6
1.6
0.5 mm
PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
3 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCAL6408ABSHP
PCAL6408APWJ
PCAL6408AHKX
PCAL6408AEXX
Package
HVQFN16
TSSOP16
XQFN16
XFBGA16
Packing method
Reel 13” Q2/T3
*standard mark SMD
Reel 13” Q1/T1
*standard mark SMD
Reel 7” Q1/T1
*standard mark SMD
Reel 7” Q1/T1
*standard mark SMD
Minimum
order quantity
6000
2500
4000
5000
Temperature
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCAL6408ABS
PCAL6408APW
PCAL6408AHK
PCAL6408AEX
4. Block diagram
PCAL6408A
INT
LP FILTER
INTERRUPT
LOGIC
ADDR
P0 to P7
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
SHIFT
REGISTER
8 BITS
I/O
PORT
V
DD(I2C-bus)
V
DD(P)
RESET
V
SS
POWER-ON
RESET
write pulse
read pulse
I/O control
002aah085
All I/Os are set to inputs at reset.
Fig 1.
Block diagram (positive logic)
PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
4 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I
2
C-bus/SMBus I/O expander
5. Pinning information
5.1 Pinning
15 V
DD(I2C-bus)
14 V
DD(P)
16 ADDR
terminal 1
index area
RESET
V
DD(I2C-bus)
ADDR
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aah086
1
2
13 SDA
12 SCL
11 INT
10 P7
9
P6
P5
8
16 V
DD(P)
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9
P4
P0
P1
P2
PCAL6408ABS
3
4
5
6
V
SS
7
P4
PCAL6408APW
P3
002aah087
Transparent top view
The exposed center pad, if used, must be
connected only as a secondary V
SS
or
must be left electrically open.
Fig 2.
Pin configuration for TSSOP16
Fig 3.
PCAL6408AHK
15 V
DD(I2C-bus)
Pin configuration for HVQFN16
16 ADDR
14 V
DD(P)
terminal 1
index area
RESET 1
P0 2
P1 3
P2 4
13 SDA
12 SCL
11 INT
10 P7
9 P6
P5 8
002aah088
P3 5
V
SS
6
Transparent top view
Fig 4.
Pin configuration for XQFN16
PCAL6408A
All information provided in this document is subject to legal disclaimers.
P4 7
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
5 of 49
